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參數(shù)資料
| 型號： | P1819H-08TT |
| 元件分類： | XO, clock |
| 英文描述： | 40 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | TSSOP-8 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 229K |
| 代理商： | P1819H-08TT |
October 2003
P1819
rev 1.0
Low Power Mobile VGA EMI Reduction IC
2 of 10
REF
PD#
VDD
XOUT
Pin Configuration
Pin Description
Pin#
1819A/B/C/D
1819E/F/G/H
Pin Name
Type
Description
1
XIN
I
Connect to externally generated clock signal or crystal.
2
VSS
P
Ground Connection. Connect to system ground.
3
SRS
I
Spread range select. Digital logic input used to select
frequency deviation. (Refer Spread Deviation
Selections Table.) This pin has an internal pull-up
resistor.
3
D_C
O
Digital logic input used to select Down (LOW) or Center
(HIGH) spread options. Refer Spread Deviation
Selections Table. This pin has an internal pull-up
resistor.
4
ModOUT
O
Spread spectrum clock output. (Refer Input Frequency
and Modulation Rate Selections Table and Spread
Deviations Selections Table)
5
REF
O
Non-modulated reference clock output of the input
frequency.
6
PD#
I
Power down control pin. Pull LOW to enable Power-
Down mode. This pin has an internal pull-up resistor.
7
VDD
P
Connect to +3.3V.
8
XOUT
O
Connect to crystal. No connect if externally generated
clock signal is used.
1
2
3
4
5
6
7
8
P1819 A/B/C/D
XIN
VSS
SRS
ModOUT
REF
1
2
3
4
5
6
7
8
P1819 E/F/G/H
XIN
VSS
D_C
ModOUT
PD#
VDD
XOUT
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