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參數(shù)資料
| 型號： | OZ6912B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Slot ACPI CardBus Controller |
| 中文描述： | 單槽ACPI的CardBus控制器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 140K |
| 代理商： | OZ6912B |
OZ6912
OZ6912-SF-1.5
Page 10
Pin Number
LQFP
93
Pin Name
Description
BGA
F13
Input
Type
Power
Rail
Socket
_Vcc
Drive
IORD#/
CAD13
I/O Read
: This output goes active (low) for I/O
reads from the OZ6912 to the socket.
CardBus Address/Data:
In CardBus mode, this
pin is the CAD bit 13.
I/O Write
: This output goes active (low) for I/O
writes from the OZ6912 to the socket.
CardBus Address/Data:
In CardBus mode, this
pin is the CAD bit 15.
Write Protect / I/O is 16-Bit:
In Memory mode,
this input is indicates the status of the write
protect switch on the PC Card. In I/O mode, this
input indicates the size of current data transfer on
the PC Card.
CardBus Clock Run:
In CardBus mode, this pin
is the CCLKRUN# signal, which starts and stops
the CardBus CCLK. To enable the CLKRUN#
signal, ExCA register 3Bh bit[3:2] must be
enabled.
Input Acknowledge:
The INPACK# function is
not applicable in PCI bus environments. This pin
is provided for Legacy card compatibility.
CardBus Request:
In CardBus mode, this pin is
the CREQ# signal.
Ready / Interrupt Request:
In Memory mode,
this input indicates that the card is ready or busy.
In I/O mode, this input indicates a card interrupt
request.
CardBus Interrupt:
In CardBus mode, this pin is
the CINT# signal. This signal is active-low and
level-sensitive.
Wait:
This pin is driven by the PC Card to delay
completion of the current cycle.
CardBus System Error:
In CardBus mode, this
pin is the CSERR# signal.
Card Detect
: These inputs indicate a card is
present in the socket. They are internally pulled
high to AUX_VCC.
CardBus Card Detect:
In CardBus mode, these
inputs are used with CVS[2:1] to detect presence
and type of card.
Card Enable 2:
This pin is driven low to control
byte/word card access. CE2# enables odd-
numbered address bytes.
CardBus Address/Data:
In CardBus mode, this
pin is the CAD bit 10.
Card Enable 1:
This pin is driven low to control
byte/word card access. CE1# enables even-
numbered address bytes. When configured for 8-
bit cards, CE1# is active and A0 is used to
indicate access of odd- or even-numbered bytes.
CardBus Command/Byte Enable:
In CardBus
mode, this pin is the CCBEO# signal.
TTL
I/O
CardBus
spec.
IOW#/
CAD15
96
F10
TTL
I/O
Socket
_Vcc
CardBus
spec.
WP/
IOIS16#/
CCLKRUN#
136
D5
TTL
I/O-PU
Socket
_Vcc
CardBus
spec.
INPACK#/
CREQ#
123
B8
-
I-PU
Socket
_Vcc
CardBus
spec.
RDY/IREQ#/
CINT#
132
D6
-
I-PU
Socket
_Vcc
CardBus
spec.
WAIT#/
CSERR#
133
A5
TTL
I-PU
Socket
_Vcc
CardBus
spec.
CD[2:1]/
CCD[2:1]#
137, 75
A4, L12
TTL
I-PU-
Schmitt
Aux_Vcc
CardBus
spec.
CE2#/
CAD10
91
G11
TTL
I/O
Socket
_Vcc
CardBus
spec.
CE1#/
CCBE0#
88
H13
TTL
I/O
Socket
_Vcc
CardBus
spec.
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