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參數(shù)資料
| 型號： | OZ6812B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ACPI CardBus Controller |
| 中文描述： | ACPI的CardBus控制器 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 105K |
| 代理商： | OZ6812B |
OZ6812
OZ6812-SF-1.5
Page 4
Pin List
Bold Text
= Normal Default Pin Name
PCI Bus Interface Pins
Pin Number
LQFP
3-5, 7-11, 15-
17, 19, 23-26,
38-41, 43, 45-
47, 49, 51-57
Pin Name
Description
BGA
Input
Type
Power
Rail
PCI_Vcc
Drive
AD[31:0]
PCI Bus Address Input / Data:
These pins
connect to PCI bus signals AD[31:0]. A Bus
transaction consists of an address phase followed
by one or more data phases.
D4, B1, C2-1,
D2, E4, D1, E3,
F3, F1, F2, G1,
H2-3, J1, H4,
M2, K4, N2,
M3, N3, K5,
N4, L5, N5, L6,
N6, M6, L7, N7,
M7, K7
E2, J2, N1, M5
TTL
I/O
PCI
Spec
C/BE[3:0]#
PCI Bus Command / Byte Enable:
The
command signaling and byte enables are
multiplexed on the same pins. During the address
phase of a transaction, C/BE[3:0]# are interpreted
as the bus commands. During the data phase,
C/BE[3:0]# are interpreted as byte enables. The
byte enables are to be valid for the entirety of
each data phase, and they indicate which bytes in
the 32-bit data path are to carry meaningful data
for the current data phase.
Cycle Frame:
This input indicates to the OZ6812
that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue.
When FRAME# is de-asserted, the transaction is
in its final phase.
Initiator Ready:
This input indicates the initiating
agent
’
s ability to complete the current data phase
of the transaction. IRDY# is used in conjunction
with TRDY#.
Target Ready:
This output indicates target
Agent's the OZ6812
’
s ability to complete the
current data phase of the transaction. TRDY# is
used in conjunction with IRDY#.
Stop:
This output indicates the current target is
requesting the master to stop the current
transaction.
Initialization Device Select:
This input is used as
a chip select during configuration read and write
transactions. This is a point-to-point signal.
IDSEL can be used as a chip select during
configuration read and write transactions.
Device Select:
This output is driven active LOW
when the PCI address is recognized as
supported, thereby acting as the target for the
current PCI cycle. The Target must respond
before timeout occurs or the cycle will terminate.
Parity Error:
The output is driven active LOW
when a data parity error is detected during a write
phase.
System Error:
This output is driven active LOW
to indicate an address parity error.
12, 27, 37, 48
TTL
I/O
PCI_Vcc
PCI
Spec
FRAME#
28
K1
TTL
I/O
PCI_Vcc
PCI
Spec
IRDY#
29
J3
TTL
I/O
PCI_Vcc
PCI
Spec
TRDY#
31
L1
TTL
I/O
PCI_Vcc
PCI
Spec
STOP#
33
K3
TTL
I/O
PCI_Vcc
PCI
Spec
IDSEL
13
E1
TTL
I
PCI_Vcc
PCI
Spec
DEVSEL#
32
J4
TTL
I/O
PCI_Vcc
PCI
Spec
PERR#
34
M1
-
TO
PCI_Vcc
PCI
Spec
SERR#
35
L2
-
TO
PCI_Vcc
PCI
Spec
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OZ6812T | ACPI CardBus Controller |
| OZ6833 | ACPI CardBus Controller |
| OZ6833B | ACPI CardBus Controller |
| OZ6833T | ACPI CardBus Controller |
| OZ962 | High-Efficiency Inverter Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OZ6812T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6833 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6833B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6833T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6912 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Slot ACPI CardBus Controller |
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