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Data Sheet Revision 1.0
Page 6
OXFW900
OXFORD SEMICONDUCTOR LTD.
56
I
CKIN
Direct clock input. Used in conjunction with an external
crystal oscillator of 24.576MHz. If a crystal is connected to
XTLI and XTLO this input must be tied low for the OXFW900
to operate. Mark space ratio of crystal oscillator must be
45:55 or better. IMPORTANT – Please refer to Application
Notes regarding clocking
Global reset for the OXFW900. Active Low.
Clock output. 24.576 MHz clock output. IMPORTANT –
Please refer to Application Notes regarding clocking
This input is used to allow the OXFW900 to reprograma
flash which has been loaded with a bad program A bad
programis defined as one that does not have the correct
interlocking mechanismfor reprogrammng flash. This pin
forces the ARMwatchdog timer to trigger thus allowing the
flash to be reprogrammed over the 1394 bus as if the flash
were blank.
‘11’ = NORMAL OPERATION. These pins have internal
pullup resistors and must be left unconnected. Other settings
are for foundry test purposes only.
23
113
IU
T_O
RESET#
CKOUT
123
IU
FORCE#
124, 125
IU
TEST[1:0]
Power and ground
2
28, 47, 94, 114
17, 24, 59, 84, 88, 121
3V3
3V3
3.3V AC VDD
3.3V DC VDD
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
Supplies 5V reference bias to all 5V tolerant I/O. All four
MUST be connected to 5V rail.
Supplies GND to output buffers in switching (AC) state
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
9, 38, 76, 112
5V
5V BIAS VDD
8, 27, 46, 67, 75, 93, 106
16, 22, 39, 55, 68, 83, 87, 107, 119
G
G
AC GND
DC GND
Table 1: Pin Descriptions
Note 1: Direction key:
I
Input
IU
Input with internal pull-up
ID
Input with external pull-down
O
Output
I/O
Bi-directional
T_I
5V tolerant input
Note 2: Power & Ground
There are two GND and three VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail). A
third rail provides 5V bias voltage to 5V tolerant IO.
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation fromthe chip.
T_O
T_I/O
G
3V3
5V
5V tolerant output
5V tolerant bi-directional
Ground
3.3V power
5V bias power