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| 型號： | ORLI10G-3BM680 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封裝： | PLASTIC, BGA-680 |
| 文件頁數(shù)： | 67/76頁 |
| 文件大?。?/td> | 1222K |
| 代理商： | ORLI10G-3BM680 |
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Lattice Semiconductor
7
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
Description
FPSC Denition
FPSCs, or eld-programmable system chips, are
devices that combine eld-programmable logic with
ASIC, or mask-programmed logic, on a single device.
FPSCs provide the time to market and the exibility of
FPGAs, the design effort savings of using soft intellec-
tual property (IP) cores, and the speed, design density,
and economy of ASICs.
FPSC Overview
Lattice's Series 4 FPSCs are created from Series 4
ORCA FPGAs. To create a Series 4 FPSC, several col-
umns of programmable logic cells (see FPGA Logic
Overview section for FPGA logic details) are added to
an embedded logic core. Other than replacing some
FPGA gates with ASIC gates, at greater than 10:1 ef-
ciency, none of the FPGA functionality is changed; all
of the Series 4 FPGA capability is retained: embedded
block RAMs, MPI, PCMs, boundary scan, etc. The col-
umns of programmable logic are replaced at the right of
the device, allowing pins from the replaced columns to
be used as I/O pins for the embedded core. The
remainder of the device pins retain their FPGA func-
tionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its
embedded core (standard-cell/ASIC gates) and its
FPGA gates. Because FPGA gates are generally
expressed as a usable range with a nominal value, the
total FPSC gate count is sometimes expressed in the
same manner. Standard-cell ASIC gates are, however,
10 to 25 times more silicon-area efcient than FPGA
gates. Therefore, an FPSC with an embedded function
is gate equivalent to an FPGA with a much larger gate
count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embed-
ded core has been enhanced to allow for a greater
number of interface signals than on previous FPSC
architectures. Compared to bringing embedded core
signals off-chip, this on-chip interface is much faster
and requires less power. All of the delays for the inter-
face are precharacterized and accounted for in the
ORCA Foundry Development System.
Series 4-based FPSCs expand this interface by provid-
ing a link between the embedded block and the multi-
master 32-bit system bus in the FPGA logic. This
system bus allows the core easy access to many of the
FPGA logic functions, including the embedded block
RAMs and the microprocessor interface.
Clock spines also can pass across the FPGA/embed-
ded core boundary. This allows for fast, low-skew clock-
ing between the FPGA and the embedded core. Many
of the special signals from the FPGA, such as DONE
and global set/reset, are also available to the embed-
ded core, making it possible to fully integrate the
embedded core with the FPGA as a system.
For even greater system exibility, FPGA conguration
RAMs are available for use by the embedded core. This
allows for user-programmable options in the embedded
core, in turn allowing for greater exibility. Multiple
embedded core congurations may be designed into a
single device with user-programmable control over
which congurations are implemented, as well as the
capability to change core functionality simply by recon-
guring the device.
ORCA Foundry Development System
The ORCA Foundry development system is used to
process a design from a netlist to a congured FPGA.
This system is used to map a design onto the ORCA
architecture and then place and route it using ORCA
Foundry's timing-driven tools. The development system
also includes interfaces to, and libraries for, other popu-
lar CAE tools for design entry, synthesis, simulation,
and timing analysis.
The ORCA Foundry development system interfaces to
front-end design entry tools and provides the tools to
produce a congured FPGA. In the design ow, the
user denes the functionality of the FPGA at two points
in the design ow: design entry and the bit stream gen-
eration stage. Recent improvements in ORCA Foundry
allow the user to provide timing requirement informa-
tion through logical preferences only; thus, the
designer is not required to have physical knowledge of
the implementation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORLI10G1BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| ORLI10G2BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| ORLI10G3BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| ORT82G5-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-2BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
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