參數(shù)資料
型號(hào)： ORLI10G-3BM416
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, BGA-416
文件頁數(shù)： 33/76頁
文件大小： 1222K
代理商： ORLI10G-3BM416
Lattice Semiconductor
39
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
Timing Characteristics (continued)
Transmit STS-48/STS-192 (2.5G/10G) Data Outputs
Figure 19 illustrates the timing for the transmit STS-48/STS-192 data stream. Both the clock and data pins are
driven with low-voltage differential signal (LVDS) output buffers. The expected clock rate is 622 MHz-850 MHz and
the transmit data is clocked out on the rising edge of the clock. In 2.5G mode, each of the four channels uses one
set of TX_CLK_OUTn with four TX_DAT_OUTn data pins. In 10G mode, only TX_CLK_OUT[0] is used with the
16 TX_DAT_OUT[15:0] pins. The timing values for the diagram in Figure 19 are given in Table 14.
5-9089.c(F)
Figure 19. Transmit Output Data Timing
Table 14. Transmit Data Output Timing
Note: This requirement is for all sources of the output clocks (e.g., RCLKSI, etc.).
It is recommended that the Tx clock be inverted by crossing the LVDS pin pair, that is, connect the
TX_CLK_OUT_P[3:0] output on the ORLI10G to the N (i.e., complement) clock input on the receiving device and
connect the TX_CLK_OUT_N[3:0] output on the ORLI10G to the P (i.e., true) clock input on the receiving device.
This is because the receiving device that will be driven by the ORLI10G typically requires that data be centered
around the clock, but the ORLI10G drives both the clock and data from the same clock edge.
Parameter
Symbol
–1
–2
–3
Unit
Min
Max
Min
Max
Min
Max
Clock Frequency
t4
—
667
—
790
—
850
MHz
Duty Cycle
—
45
55
45
55
45
55
%
Data Delay from Clock Edge
t5
–300
300
–225
225
–210
210
ps
Data Rise Time: 20%—80%
t6
100
200
100
200
100
200
ps
Data Fall Time: 80%—20%
t7
100
200
100
200
100
200
ps
t5
TX_DAT_OUT_P[15:0]
t6
t7
TX_CLK_OUT_N[3:0]
t4
TX_CLK_OUT_P[3:0]
TX_DAT_OUT_N[15:0]
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