- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383713 > OR2C40A-7PS240I (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | OR2C40A-7PS240I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 54/192頁 |
| 文件大小： | 3148K |
| 代理商： | OR2C40A-7PS240I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當(dāng)前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁
54
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 2 FPGAs
Special Function Blocks
(continued)
Boundary Scan
The increasing complexity of integrated circuits (ICs)
and IC packages has increased the difficulty of testing
printed-circuit boards (PCBs). To address this testing
problem, the IEEEstandard 1149.1 - 1990 (IEEEStan-
dard Test Access Port and Boundary-Scan Architec-
ture) is implemented in the ORCA series of FPGAs. It
allows users to efficiently test the interconnection
between integrated circuits on a PCB as well as test
the integrated circuit itself. The IEEE1149.1 standard
is a well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.
The IEEE1149.1 standard defines a test access port
(TAP) that consists of a 4-pin interface with an optional
reset pin for boundary-scan testing of integrated cir-
cuits in a system. The ORCA series FPGA provides
four interface pins: test data in (TDI), test mode select
(TMS), test clock (TCK), and test data out (TDO). The
PRGM
pin used to reconfigure the device also resets
the boundary-scan logic.
The user test host serially loads test commands and
test data into the FPGA through these pins to drive out-
puts and examine inputs. In the configuration shown in
Figure 47, where boundary scan is used to test ICs,
test data is transmitted serially into TDI of the first
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of
the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
operate in the same state. In other configurations, mul-
tiple scan paths are used instead of a single ring. When
multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals.
Figure 48 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.
Fig.34.a(F).1C
Key:
BSC = boundary-scan cell, BDC = bidirectional data cell,
and DCC = data control cell.
Figure 47. Printed-Circuit Board with Boundary-
Scan Circuitry
The boundary-scan support circuit shown in Figure 48
is the 497AA Boundary-Scan Master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general microprocessor interface
and provides parallel-to-serial/serial-to-parallel conver-
sion, as well as three 8K data buffers.
SCAN
OUT
TDI
TMS
TCK
TDO
U2
SEE ENLARGED VIEW BELOW
PLC
ARRAY
SCAN
IN
TDO TCK TMS TDI
TAPC
BYPASS
REGISTER
INSTRUCTION
REGISTER
BDC
BSC
P_IN
P_OUT
P_TS
SCAN
IN
PT[ij]
ENLARGED VIEW
TDI
TDO
TMS
TCK
U1
TDI
TDO
TMS
TCK
U4
TDI
TDO
TMS
TCK
U3
TDI
TDO
TMS
TCK
net a
net b
net c
s
DCC
SCAN
OUT
DCC
BSC
P_IN
P_OUT
P_TS
SCAN
IN
PB[ij]
BDC
SCAN
OUT
BDC
BSC
P_IN
P_OUT
P_TS
PR[ij]
DCC
SCAN
OUT
BSC
P_IN
P_OUT
P_TS
PL[ij]
SCAN
IN
DCC
BDC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C40A-7PS304 | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 820pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-20%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated SnPb; Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate |
| OR2C40A-7PS304I | Field-Programmable Gate Arrays |
| OR2C40A-7PS352 | Field-Programmable Gate Arrays |
| OR2C40A-7PS352I | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 8200pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated SnPb; Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate |
| OR2C40A-7PS432 | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2T04A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-2BA100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-2BA100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-2BA144 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-2BA144I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。