- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383717 > OR2C40A-3J240I (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | OR2C40A-3J240I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 27/192頁 |
| 文件大小： | 3148K |
| 代理商： | OR2C40A-3J240I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁
Lucent Technologies Inc.
27
Data Sheet
June 1999
ORCA Series 2 FPGAs
Programmable Input/Output Cells
(continued)
Regardless of the power supply that the V
DD
5 pins are
connected to (5 V or 3.3 V), the OR2TxxA devices will
drive the pin to the 3.3 V levels when the output buffer
is enabled. If the other device being driven by the
OR2TxxA device has TTL-compatible inputs, then the
device will not dissipate much input buffer power. This
is because the OR2TxxA output is being driven to a
higher level than the TTL level required. If the other
device has a CMOS-compatible input, the amount of
input buffer power will also be small. Both of these
power values are dependent upon the input buffer char-
acteristics of the other device when driven at the
OR2TxxA output buffer voltage levels.
The 2TxxA device has internal programmable pull-ups
on the I/O buffers. These pull-up voltages are always
referenced to V
DD
. This means that the V
DD
5 voltage
has no effect on the value of the pull-up voltage at the
pad. This voltage level is always sufficient to pull the
input buffer of the 2TxxA device to a high state. The pin
on the 2TxxA device will be at a level 1.0 V below V
DD
(minimum of 2.0 V with a minimum V
DD
of 3.0 V). This
voltage is sufficient to pull the external pin up to a 3.3 V
CMOS high-input level (1.8 V min) or a TTL high-input
level (2.0 V min) in a 5 V tolerant system, but it will
never pull the pad up to the V
DD
5 rail. Therefore, in a
5 V tolerant system using 5 V CMOS parts, care must
be taken to evaluate the use of these pull-ups to pull
the pin of the 2TxxA device to a typical 5 V CMOS
high-input level (2.2 V min).
For more information on 5 V tolerant I/Os, please see
ORCA
Series 5 V Tolerant I/OsApplication Note
(AP99-027FPGA), May 1999.
5 V Tolerant I/O (OR2TxxB)
The I/O on the OR2TxxB Series devices allow intercon-
nection to both 3.3 V and 5 V device (selectable on a
per-pin basis). Unlike the OR2TxxA family, when inter-
faceing into a 5 V signal, it no longer requires a V
DD
5
supply.
The OR2TxxB devices will drive the pin to the 3.3 V lev-
els when the output buffer is enabled. If the other
device being driven by the OR2TxxB device has TTL-
compatible inputs, then the device will not dissipate
much input buffer power. This is because the OR2TxxB
output is being driven to a higher level than the TTL
level required. If the other device has a CMOS-compat-
ible input, the amount of input buffer power will also be
small. Both of these power values are dependent upon
the input buffer characteristics of the other device when
driven at the OR2TxxB output buffer voltage levels.
The OR2TxxB device has internal programmable pull-
ups on the I/O buffers. These pull-up voltages are
always referenced to V
DD
and are always sufficient to
pull the input buffer of the OR2TxxB device to a high
state. The pin on the OR2TxxB device will be at a level
1.0 V below V
DD
(minimum of 2.0 V with a minimum
V
DD
of 3.0 V). This voltage is sufficient to pull the exter-
nal pin up to a 3.3 V CMOS high-input level (1.8 V, min)
or a TTL high input level (2.0 V, min) in a 5 V tolerant
system. Therefore, in a 5 V tolerant system using 5 V
CMOS parts, care must be taken to evaluate the use of
these pull-ups to pull the pin of the OR2TxxB device to
a typical 5 V CMOS high-input level (2.2 V, min).
PCI Compliant I/O
The I/O on the OR2TxxB Series devices allows compli-
ance with PCI local bus (Rev. 2.1) 5 V and 3.3 V signal-
ing environments. The signaling environment used for
each input buffer can be selected on a per-pin basis.
The selection provides the appropriate I/O clamping
diodes for PCI compliance.
OR2TxxB devices have 5 V tolerant I/Os as previously
explained, but can optionally be selected on a pin-by-
pin basis to be PCI bus 3.3 V signaling compliant (PCI
bus 5 V signaling compliance occurs in 5 V tolerant
operation mode). Inputs may have a pull-up or pull-
down resistor selected on an input for signal stabiliza-
tion and power management. Input signals in a PIO
can be passed to PIC routing on any of three paths,
two general signal paths into PIC routing, and/or a fast
route into the clock routing system.
OR2TxxA series devices are only compliant in 3.3 V
PCI Local Bus (Rev 2.1) signalling environments.
OR2CxxA devices are only compliant in 5 V PCI Local
Bus (Rev 2.1) signalling environments.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C40A-3J352I | Field-Programmable Gate Arrays |
| OR2C40A-3M208 | Field-Programmable Gate Arrays |
| OR2C40A-3M208I | Field-Programmable Gate Arrays |
| OR2C40A-3M240 | Field-Programmable Gate Arrays |
| OR2C40A-3M240I | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C40A3PS208I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A3PS240I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A3PS304I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4BC432-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR2C40A4PS208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。