參數(shù)資料
型號(hào)： OQ2535HP
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SDH/SONET STM16/OC48 multiplexer(SDH/SONET STM16/OC48多路復(fù)用器)
中文描述： MUX/DEMUX, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, SOT-470-1, HLQFP-100
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 95K
代理商： OQ2535HP
1999 Oct 04
7
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
FUNCTIONAL DESCRIPTION
The OQ2535HP is a 32-channel multiplexer intended for
use in STM16/OC48 applications. It multiplexes
32
×
78 Mbits/s input channels onto a single 2.5 Gbits/s
output channel.
The multiplexing is performed in two stages. The 32 input
channels are fed into four 8 : 1 multiplexers to generate
four 622 Mbits/s channels. These four channels are then
combined into a single 2.5 Gbits/s data stream.
The ENL control input is used for switching between
normal and loop modes. When loop mode is enabled,
(ENL = LOW), the outputsignalis switchedto DLOOP and
DLOOPQ (these outputs could be connected to the
DLOOP and DLOOPQ inputs on the OQ2536HP
demultiplexer to form part of a test loop).
The 2.5 GHz clock at CIN and CINQ is used as the system
reference. It is divided down to 78 MHz and made
available on the CDIV TTL output for timing the input data
(D0 to D31).
Low bit rate stage: 4
×
8 : 1 MUX
This part of the circuit consists of four 8-bit shift registers,
each acting as an 8 : 1 multiplexer, together with a
synchronization block.
The 32 data input signals are loaded into the shift registers
before being shifted out on a 622 MHz clock.
The load pulse for the shift registers is generated in the
synchronization block. The inputs SYNSEL1 and
SYNSEL2 can be used to adjust the phase of the load
pulse with respect to the input data (see Table 3) to
synchronize the data and clock signals.
High bit rate stage: 4 : 1 MUX
The four 622 Mbits/s data outputs from the low bit rate
stage are combined into a single 2.5 Gbits/s data stream
in two stages: two 2 : 1 multiplexers are used to generate
two 1244 Mbits/s data streams; these signals are then fed
into a third 2 : 1 multiplexer to generate the 2.5 Gbits/s
data stream.
The 2.5 Gbits/s serial data stream is passed either to the
DOUT and DOUTQ outputs (normal mode), or to the
DLOOP and DLOOPQ outputs (loop mode). The output
sequence is D31 (MSB) to D0 (LSB). Data and clock
output buffers are terminated internally with 100
resistors to GND and are capable of driving 50
loads.
The unused output buffers are switched off to help
minimize power dissipation.
The outputs CLOOP, CLOOPQ, DLOOP and DLOOPQ
are terminated internally with 100
resistors to GND and
are specifically designed to drive 50
printed-circuit
board transmission lines.
The 2.5 GHz clock connected to CIN and CINQ is
terminated internally with 50
to GND.
Power supply connections
The power supply pins need to be individually decoupled
using chip capacitors mounted as close as possible to the
IC. If multiple decoupling capacitors are used for a single
supply node, they must be placed close to each other to
avoid RF resonance.
Tominimize lowfrequencyswitching noise in thevicinity of
the OQ2535HP, all power supply lines should be filtered
once by an LC-circuit with a low cut-off frequency (as
shown in the application diagram, Fig.6). V
CC(T)
needs to
be filtered separately via an LC-circuit because of the high
switching currents present at the CDIV TTL output. As this
current contains only 78 MHz harmonics, filtering can be
achieved with relatively small values of L and C.
Ground connection
The ground connection on the printed-circuit board needs
to be a large copper area fill connected to a common
ground plane with low inductance.
RF connections
A coupled stripline or microstrip with an odd mode
characteristic impedance of 50
(nominal value) should
be used for the RF connections on the printed-circuit
board. The connections should be kept as short as
possible. This applies to the CML differential line pairs CIN
and CINQ, DOUT and DOUTQ, COUT and COUTQ,
DLOOP and DLOOPQ, and CLOOP and CLOOPQ. In
addition, the following lines should not vary in length by
more than 5 mm:
CIN and CINQ
DOUT, DOUTQ, COUT and COUTQ
DLOOP, DLOOPQ, CLOOP and CLOOPQ.
Interface to transmit logic
The 78 Mbits/s interface lines, CDIV and D0 to D31,
should not vary in length by more than 20 mm.
The parasitic capacitance of these lines should be as
small as possible.
相關(guān)PDF資料
PDF描述
OQ2536HP SDH/SONET STM16/OC48 demultiplexer(SDH/SONET STM16/OC48多路分解器)
OQ2538HP SDH/SONET STM16/OC48 main amplifiers(SDH/SONET STM16/OC48主要放大器)
OQ2538U SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U SDH/SONET STM16/OC48 main amplifiers(SDH/SONET STM16/OC48主要放大器)
OQ2541BHP CLOCK/DATA RECOVERY|BIPOLAR|QFP|48PIN|PLASTIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OQ2536HP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:SDH/SONET STM16/OC48 demultiplexer
OQ2538HP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:SDH/SONET STM16/OC48 main amplifiers
OQ2538HP_97 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:SDH/SONET main amplifier
OQ2538HPS1 制造商:NXP Semiconductors 功能描述:
OQ2538U 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:SDH/SONET STM16/OC48 main amplifiers
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