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參數(shù)資料
| 型號(hào)： | OPA655U |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Wideband, Unity Gain Stable, FET-Input OPERATIONAL AMPLIFIER |
| 中文描述： | 寬帶，單位增益穩(wěn)定，F(xiàn)ET輸入運(yùn)算放大器 |
| 文件頁(yè)數(shù)： | 13/14頁(yè) |
| 文件大?。?/td> | 222K |
| 代理商： | OPA655U |
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13
OPA655
THERMAL CONSIDERATIONS
The OPA655 will not require heatsinking under most oper-
ating conditions. Maximum desired junction temperature
will limit the maximum allowed internal power dissipation
as described below. In no case should the maximum junction
temperature be allowed to exceed +175
°
C.
Operating junction temperature (T
J
) is given by
T
A
+ P
D
θ
JA
. The total internal power dissipation (P
D
) is a
combination of the quiescent power plus the power dissi-
pated in the output stage to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. P
DL
will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is a
fixed DC voltage equal to 1/2 of either supply voltage
(assuming equal bipolar supplies). Under this condition
P
DL
= V
S2
/(4 R
L
) where R
L
includes feedback network
loading. Note that it is the power dissipated in the output
stage and not in the load that determines internal power
dissipation. As an example, compute the maximum T
J
for
the OPA655U at G = +2, R
L
= 100
, R
F
= 100
,
±
V
S
=
±
5V, and at the specified maximum T
A
= 85
°
C. P
D
= 10V
31mA + (5
2
)/[4 (100 || 200)] = 404mW. Maximum T
J
=
85
°
C + 0.404W 125
°
C/W = 136
°
C.
LAYOUT AND INTERCONNECT
CONSIDERATIONS
Achieving optimum performance with a high frequency
amplifier like the OPA655 requires careful attention to
layout parasitics and selection of external components. Sug-
gestions include:
Minimize parasitic capacitance
to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the non-
inverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes. Other-
wise, ground and power planes should be unbroken else-
where on the board.
Minimize the distance
(< 0.25") from the four power pins
to high frequency 0.1
μ
F decoupling capacitors. At the
pins, the ground and power plane layout should not be in
close proximity to the signal I/O pins. The OPA655 may
be operated with only pins 4 and 7 connected as supply
pins allowing a direct replacement into existing 8 pin op
amp pinouts. Connecting the output stage power pins
separately, and decoupling them, will give the best distor-
tion and settling performance. Avoid narrow power and
ground traces to minimize inductance between the pins
and the decoupling capacitors. Larger (2.2
μ
F to 6.8
μ
F)
decoupling capacitors, effective at lower frequencies,
should also be used. These may be placed somewhat
farther from the device and may be shared among several
devices in the same area of the PC board.
DIFFERENTIAL GAIN AND DIFFERENTIAL PHASE
The OPA655 provides one of the lowest dG/dP errors of any
op amp. This specification is the change in the small signal
gain and phase for a composite video color carrier frequency
when the output voltage is slowly ramped over the lumi-
nance range. The specifications show less than 0.01%/0.01
°
for positive NTSC into a single video load. This level of
performance challenges the accuracy of commercially avail-
able video test equipment. Measurements were taken using
an HP9480 IC parametric test system.
OUTPUT DRIVE CAPABILITY
The guaranteed output current of
±
28mA will drive a 100
load over the full guaranteed output voltage range of
±
2.8V.
These minimum performance levels are only applicable at
cold temperatures, with higher output voltage and current
available in most applications. Many demanding high speed
applications, such as driving ADC’s, require amplifiers with
low, broadband, output impedance. As shown in Figure 13,
the OPA655 maintains a very low closed loop output imped-
ance over frequency. Closed loop output impedance in-
creases with frequency as the loop gain rolls off.
FIGURE 12. 5MHz Harmonic Distortion vs Load Resistance.
–50
–60
–70
–80
–90
–100
10
100
1000
Load Resistance (
)
H
2f
O
3f
O
V
O
= 2Vp-p, G = +5, f
O
= 5MHz
FIGURE 13. Small-Signal Output Impedance vs Frequency.
10
1
0.01
0.1
0.001
10k
100k
1M
10M
100M
Frequency (Hz)
O
)
G = +1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OPA656 | 制造商:BB 制造商全稱:BB 功能描述:Precision, High-Speed Transimpedance Amplifier |
| OPA656-DIE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:WIDEBAND, UNITY-GAIN STABLE, FET-INPUT OPERATIONAL AMPLIFIER |
| OPA656MDREP | 功能描述:IC OPAMP VFB 230MHZ SGL 8SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:160 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:10 V/µs 增益帶寬積:9MHz -3db帶寬:- 電流 - 輸入偏壓:1pA 電壓 - 輸入偏移:250µV 電流 - 電源:730µA 電流 - 輸出 / 通道:28mA 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V，±1.35 V ~ 2.75 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC N 包裝:管件 |
| OPA656N | 制造商:Texas Instruments 功能描述:OP AMP VFB FET I/P SOT-23-5 656 制造商:Texas Instruments 功能描述:OP AMP, VFB FET I/P, SOT-23-5, 656 制造商:Texas Instruments 功能描述:OP AMP, VFB FET I/P, SOT-23-5, 656; Op Amp Type:Wideband; No. of Amplifiers:1; Slew Rate:290V/s; Supply Voltage Range:10V to 12V, 6V; Amplifier Case Style:SOT-23; No. of Pins:5; Bandwidth:500MHz; Operating Temperature Min:-40C; |
| OPA656N | 制造商:Texas Instruments 功能描述:OP AMP VFB FET I/P SOT-23-5 656 |
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