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參數(shù)資料
| 型號(hào)： | OPA3682U |
| 英文描述： | Triple, Wideband, Fixed Gain BUFFER AMPLIFIER With Disable |
| 中文描述： | 三，寬帶，固定增益緩沖放大器具有禁用 |
| 文件頁(yè)數(shù)： | 18/19頁(yè) |
| 文件大小： | 234K |
| 代理商： | OPA3682U |
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18
OPA3682
DISABLE OPERATION
The OPA3682 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA3682 will operate normally.
To disable, the control pin must be asserted low. Figure 7
shows a simplified internal circuit for the disable control
feature.
The transition edge rate (dV/dt) of the DIS control line will
influence this glitch. For the plot of Figure 8, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
V
DIS
pin from a higher speed logic line. If extremely fast
transition logic is used, a 2k
series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring an adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA3682,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175
°
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at a
voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition P
DL
= V
S2
/(4 R
L
), where R
L
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA3682 in the circuit of Figure 1 operating at the maxi-
mum specified ambient temperature of +85
°
C with all three
outputs driving a grounded 100
load to +2.5V:
P
D
= 10V 19.8mA + 3 (5
2
/(4 (100
|| 800
)) = 409mW
Maximum T
J
= +85
°
C + (0.41W 100
°
C/W) = 126
°
C
This worst-case condition is within the maximum junction
temperature. Normally, this extreme case will not be en-
countered. Careful attention to internal power dissipation is
required.
In normal operation, base current to Q1 is provided through
the 110k
resistor while the emitter current through the
15k
resistor sets up a voltage drop that is inadequate to turn
on the two diodes in Q1’s emitter. As V
DIS
is pulled low,
additional current is pulled through the 15k
resistor even-
tually turning on these two diodes (
≈
100
μ
A). At this point,
any additional current pulled out of V
DIS
goes through those
diodes holding the emitter-base voltage of Q1 at approxi-
mately zero volts. This shuts off the collector current out of
Q1, turning the amplifier off. The supply current in the
disable mode is only that required to operate the circuit of
Figure 7. Additional circuitry ensures that turn-on time
occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA3682 is operating in a gain of +1,
this will show a very high impedance (4pF || 1M
) at the
output and exceptional signal isolation. If operating at a gain
greater than +1, the total feedback network resistance (R
F
+
R
G
) will appear as the impedance looking back into the
output but, the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (R
F
+ R
G
) giving relatively poor input to
output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 8
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output pin
is plotted along with the DIS pin voltage.
25k
110k
15k
I
Control
–V
S
+V
S
V
DIS
Q1
FIGURE 7. Simplified Disable Control Circuit.
FIGURE 8. Disable/Enable Glitch.
40
20
0
–20
–40
Time (20ns/div)
O
Output Voltage
(0V Input)
V
DIS
0.2V
4.8V
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| OPA3682U/2K5 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog Buffer/Voltage Follower |
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| OPA3684ID | 制造商:Texas Instruments 功能描述:OPERATIONAL AMPLIFIER ((NW)) 制造商:Texas Instruments 功能描述:IC, OP-AMP, 250MHZ, 780V/ uS, SOIC-14 |
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