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2
OPA2607
SPECIFICATIONS: V
S
=
±
12V
R
F
= 1.21k
, R
L
= 100
, and G = +8, unless otherwise noted.
OPA2607H, U, N
TYP
GUARANTEED
0
°
C to
70
°
C
(3)
–40
°
C to
+85
°
C
(3)
MIN/
MAX
LEVEL
(1)
TEST
PARAMETER
CONDITIONS
+25
°
C
+25
°
C
(2)
UNITS
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (V
O
= 0.5Vp-p)
G = +1, R
F
= 1.50k
G = +2, R
F
= 1.43k
G = +4, R
F
= 1.37k
G = +8, R
F
= 1.21k
G = +8, V
O
= 0.5Vp-p
G = +8, V
O
= 20Vp-p
G = +8, V
O
= 20V Step
G = +8, V
= 0.5V Step
V
= 2Vp-p, 1MHz, R
L
= 100
V
O
= 20Vp-p, 150kHz, R
L
= 150
35
28
25
25
6
13
600
14
77
75
1.7
11
15
0.01
0.01
–60
MHz
MHz
MHz
MHz
MHz
MHz
V/
μ
s
ns
dB
dB
nV/
√
Hz
pA/
√
Hz
pA/
√
Hz
%
degrees
dB
typ
typ
typ
min
typ
min
min
min
min
min
max
max
max
typ
typ
typ
C
C
C
B
C
B
B
B
B
B
B
B
B
C
C
C
19
18
17
Bandwidth for 0.1dB Gain Flatness
Large-Signal Bandwidth
Slew Rate
Rise/Fall Time
Spurious Free Dynamic Range
(4)
10.6
470
18
66
70
2.0
13
17
9.0
400
20
60
58
2.6
13
17
7.9
350
21
57
57
2.7
13
17
Input Voltage Noise
Non-Inverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
Channel-to-Channel Crosstalk
NTSC, G = +2, R
L
= 150
NTSC, G = +2, R
L
= 150
f = 1MHz
DC PERFORMANCE
(5)
Open-Loop Transimpedance Gain
Input Offset Voltage
Average Offset Voltage Drift
Non-Inverting Input Bias Current
Average Non-Inverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
V
O
= 0V, R
= 100
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
950
±
1.5
440
±
7
390
±
8
–20
±
15
–70
±
58
–380
310
±
8.5
–25
±
20
–100
±
70
–425
k
mV
μ
V/
°
C
μ
A
nA/
°
C
μ
A
nA/
°
C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±
3
±
12
±
4
±
40
INPUT
Common-Mode Input Range
(CMIR)
Common-Mode Rejection Ratio
(CMRR)
Non-Inverting Input Impedance
Inverting Input Resistance
±
10.3
64
250 || 4
33
±
10.0
53
±
9.9
52
±
9.8
51
V
dB
min
min
typ
typ
A
A
C
C
V
CM
= 0V
k
|| pF
Open-Loop
OUTPUT
Voltage Output Swing
No Load, Hard Limit
R
L
= 100
, Hard Limit
R
L
= 150
, SFDR > 67dB, 150kHz
V
O
= 0
V
= 0
G = +8, f
≤
10kHz
±
11.2
±
10.5
±
10.2
310
250
0.02
±
10.9
±
9.9
±
10.8
±
9.8
±
10.7
±
9.7
V
V
V
min
min
typ
min
min
typ
A
A
C
A
A
C
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
210
180
175
150
140
110
mA
mA
Power Control
(SO-14 only)
Maximum Logic 0
Minimum Logic 1
Logic Input Current
Supply Current at Full Power
Supply Current at Power Cutback
Supply Current at Idle Power
Supply Current at Shutdown
Output Impedance in Idle Power
Output Impedance in Shutdown
Shutdown Isolation
Maximum Adjusted Quiescent Current
Minimum Adjusted Quiescent Current
DIG_REF = Gnd
A0, A1
A0, A1
0V to 4.5V
A0 = 1, A1 = 1, I
ADJ
= open
A0 = 0, A1 = 1, I
ADJ
= open
A0 = 1, A1 = 0, I
ADJ
= open
A0 = 0, A1 = 0, I
= open
Closed-Loop, f < 1MHz
0.8
2
60
16
13
3.8
1.3
0.7
V
V
μ
A
mA
mA
mA
mA
max
min
max
typ
typ
typ
typ
typ
typ
typ
typ
typ
C
C
C
C
C
C
C
C
C
C
C
C
350 || 17
75
20
12
k
|| pF
dB
mA
mA
G = +8, 1MHz
A0 = 1, A1 = 1, I
ADJ
at +V
S
A0 = 1, A1 = 1, I
ADJ
at –V
S
POWER SUPPLY
Minimum Operating Voltage
Specified Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
±
6
±
6
±
6
V
V
V
min
typ
max
max
min
min
B
C
A
A
A
A
±
12
±
16
16.8
15.2
61
±
16
17
13.8
59
±
16
17.5
13.3
57
Total Both Channels, Full Power
Total Both Channels, Full Power
f
≤
10kHz
16
16
68
mA
mA
dB
TEMPERATURE RANGE
Specification: H, U, N
Thermal Resistance,
θ
H
PSO-8 Power Package
(6)
U
SO-8
N
PSO-14 Power Package
(6)
–40 to +85
°
C
typ
C
Junction-to-Ambient
50
125
45
°
C/W
°
C/W
°
C/W
typ
typ
typ
C
C
C
NOTES: (1) Test Levels: (A) 100% tested at 25
°
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25
°
C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +40
°
C at high temperature limit for over temperature guaranteed specifications. (4) Single amplifier SFDR limited by 2nd Harmonic.
Differential SFDR will be limited by 3rd Harmonic and will be > 15dB higher. (5) Current is considered positive out of node. V
is the input common-mode voltage.
(6) Slug in power package connected to –V
S
plane at least 2" x 2" (50mm x 50mm) in size. See the Board Layout Guidelines Section.