參數(shù)資料
型號(hào): ONET3301PARGT
廠商: Texas Instruments, Inc.
元件分類: 運(yùn)動(dòng)控制電子
英文描述: 155-MBPS TO 3.3-GBPS LIMITING AMPLIFIER
中文描述: 155 - Mbps到3.3 Gbps的限幅放大器
文件頁數(shù): 2/12頁
文件大小: 260K
代理商: ONET3301PARGT
SLLS603B MARCH 2004 REVISED DECEMBER 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
block diagram
A simplified block diagram of the ONET3301PA is shown in Figure 1.
This compact, low power 3.3-Gbps limiting amplifier consists of a high-speed data path with offset cancellation
block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.
The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.
Input Buffer
DOUT+
DOUT
DIN+
DIN
+
Gain Stage
+
+
+
COC2
COC1
DISABLE
LOS
TH
VCC
GND
OUTPOL
Bandgap Voltage
Reference and
Bias Current
Generation
Gain Stage
Gain Stage
Loss of Signal
and
RSSI Detection
Offset
Cancellation
VCCO
RSSI
CML
Output
Buffer
+
Figure 1. Block Diagram
high-speed data path
The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2
×
50-
on-chip line termination to VCC, three gain stages, which provide
the required typical gain of about 50 dB and a CML output stage. The amplified data output signal is available
at the output pins DOUT+/DOUT–, which provide 2
×
50-
back-termination to VCCO. The output stage also
includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function,
controlled by the signal applied to the DISABLE input pin.
An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even
for small input data signals.
The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.
For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
loss of signal and RSSI detection
The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block
a signal is generated, which is linear proportional to the input amplitude over a wide input voltage range. This
signal is available at the RSSI output pin.
Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means
of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of
signal is indicated at the LOS pin.
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