參數(shù)資料
型號(hào): OM4068H
廠商: NXP Semiconductors N.V.
元件分類: LCD驅(qū)動(dòng)器
英文描述: LCD driver for low multiplex rates
封裝: OM4068H/2<SOT307-2 (QFP44)|<<http://www.nxp.com/packages/SOT307-2.html<1<Always Pb-free,;
文件頁數(shù): 14/28頁
文件大小: 125K
代理商: OM4068H
1998 Jun 18
14
Philips Semiconductors
Product specification
LCD driver for low multiplex rates
OM4068
Display latch
The 96-bit display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch and the LCD segment outputs. An LCD segment is
activated when the corresponding data bit in the display
latch is HIGH.
Display latches are in HOLD mode (SCE HIGH) during the
shift operation to maintain the display data constant.
Data are latched into the display latch with the internal
frame clock. Thus there is a delay of up to one half frame
before new data are latched after signal SCE returns to
zero.
Timing
The timing of the OM4068 organizes the internal data flow
of the device. This includes the transfer of display data
from the shift register to the display segments outputs.
The timing also generates the LCD frame frequency which
is derived from the clock frequency generated in the
internal clock generator:
f
2400
f
fr(LCD)
------------
=
Shift register configuration
Fig.9 Display data bit position in shift register.
handbook, full pagewidth
1
D1A
D32A
SDIN
SDOUT
32
96-bit shift register
64
96
32-bit register
driving mode: static; (M1, M0) = 01
driving mode: duplex (1 : 2); (M1, M0) = 10
D1A
D1B
D32A
D32B
SDIN
32-bit register
SDOUT
32-bit register
driving mode: triplex (1 : 3); (M1, M0) = 11
D1A
D1B
D32A
D32B
SDIN
32-bit register
32-bit register
D1C
D32C
MBK823
SDOUT
32-bit register
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