參數(shù)資料
型號(hào): NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁數(shù): 22/85頁
文件大小: 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
29
REV 1.0
06 / 2010
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence
and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full
interleave address ordering is supported, however, sequential address ordering is nibble based for ease of
implementation. The burst type, either sequential or interleaved, is programmable and defined by the address
bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or
write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write
burst when burst length = 8 is used, see the
“Burst Interruption “section of this datasheet. A Burst Stop
command is not supported on DDR2 SDRAM devices.
Bust Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
x
0
0,
1,
2,
3
0,
1,
2,
3
x
0
1
1,
2,
3,
0
1,
0,
3,
2
x
1
0
2,
3,
0,
1
2,
3,
0,
1
x
1
3,
0,
1,
2
3,
2,
1,
0
8
0
0,
1,
2,
3,
4,
5,
6,
7
0,
1,
2,
3,
4,
5,
6,
7
0
1
1,
2,
3,
0,
5,
6,
7,
4
1,
0,
3,
2,
5,
4,
7,
6
0
1
0
2,
3,
0,
1,
6,
7,
4,
5
2,
3,
0,
1,
6,
7,
4,
5
0
1
3,
0,
1,
2,
7,
4,
5,
6
3,
2,
1,
0,
7,
6,
5,
4
1
0
4,
5,
6,
7,
0,
1,
2,
3
4,
5,
6,
7,
0,
1,
2,
3
1
0
1
5,
6,
7,
4,
1,
2,
3,
0
5,
4,
7,
6,
1,
0,
3,
2
1
0
6,
7,
4,
5,
2,
3,
0,
1
6,
7,
4,
5,
2,
3,
0,
1
7,
4,
5,
6,
3,
0,
1,
2
7,
6,
5,
4,
3,
2,
1,
0
Note:
1) Page length is a function of I/O organization
64Mb X 16 organization (CA0-CA9); Page Size = 2K Byte; Page Length = 1024
128Mb X 8 organization (CA0-CA9 ); Page Size = 1K Byte; Page Length = 1024
256Mb x 4 organization (CA0-CA9, CA11); Page Size = 1K Byte; Page Length = 2048
2) Order of burst access for sequential addressing is "nibble-based" and therefore
different from SDR or
DDR components
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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