參數(shù)資料
型號(hào): NL17SHT126P5T5G
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/5頁(yè)
文件大?。?/td> 0K
描述: IC GATE NONINV BUFFER SOT953
標(biāo)準(zhǔn)包裝: 8,000
邏輯類(lèi)型: 緩沖器/線路驅(qū)動(dòng)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 1
輸出電流高,低: 8mA,8mA
電源電壓: 3 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: SOT-953
供應(yīng)商設(shè)備封裝: SOT-953
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2011
August, 2011 Rev. 0
1
Publication Order Number:
NL17SHT126/D
NL17SHT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTLCompatible Inputs
The NL17SHT126 is a single gate noninverting 3state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The NL17SHT126 requires the 3state control input (OE) to be set
Low to place the output into the high impedance state.
The device input is compatible with TTLtype input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logiclevel translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the highvoltage power supply.
The NL17SHT126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the NL17SHT126 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOSCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
These are PbFree Devices
Figure 1. Pinout (Top View)
IN A
OUT Y
VCC
OE
IN A
OUT Y
GND
OE
Figure 2. Logic Symbol
1
2
3
4
5
PIN ASSIGNMENT
1
2
3OE
IN A
GND
4
5VCC
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
H
X
A Input
Y Output
L
H
Z
OE Input
H
L
http://onsemi.com
MARKING
DIAGRAM
SOT953
CASE 527AE
R
= Specific Device Code
M
= Month Code
RM
1
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