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參數(shù)資料
| 型號： | NCP7662P |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | INDUCTORLESS VOLTAGE CONVERTER |
| 中文描述： | SWITCHED CAPACITOR REGULATOR, 35 kHz SWITCHING FREQ-MAX, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 152K |
| 代理商： | NCP7662P |
NCP7662
http://onsemi.com
6
Figure 5. Paralleling Devices
4
1
2
3
8
7
6
5
N
C1
+
–
4
1
2
3
8
7
6
5
N
C1
+
–
+
C2
RL
V+
Cascading Devices
The NCP7662 may be cascaded as shown to produce
larger negative multiplication of the initial supply voltage.
However, due to the finite efficiency of each device, the
practical limit is 10 devices for light loads. The output
voltage is defined by:
VOUT
n(VIN)
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual NCP7662
ROUT values.
Figure 6. Cascading Devices
for Increased Output Voltage
10
μ
F
4
1
2
3
8
7
6
5
N
“1”
VOUT
+
4
1
2
3
8
7
6
5
N
“n”
+
+
10
μ
F
10
μ
F
*VOUT = –nV+
10
μ
F
V+
Changing the NCP7662 Oscillator Frequency
It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
This is achieved by one of several methods described below:
By connecting the Boost Pin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence the
oscillator frequency is increased by approximately 3–1/2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount
applications where capacitor size and cost are critical.
Smaller capacitors, e.g., 0.1
μ
F, can be used in conjunction
with the Boost Pin in order to achieve similar output currents
compared to the device free running with C1 = C2 = 1
μ
F or
10
μ
F. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).
Increasing the oscillator frequency can also be achieved
by overdriving the oscillator from an external clock as
shown in Figure 7. In order to prevent device latchup, a 1 k
resistor must be used in series with the clock output. In a
situation where the designer has generated the external clock
frequency using TTL logic, the addition of a 10 k
pullup
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be 1/2 of the clock frequency. Output transitions occur
on the positive–going edge of the clock.
Figure 7. External Clocking
10
μ
F
4
1
2
3
8
7
6
5
N
VOUT
+
+
10
μ
F
CMOS
GATE
1 k
V+
V+
It is also possible to increase the conversion efficiency of
the NCP7662 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 8. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the pump
(C1) and reservoir (C2) capacitors; this is overcome by
increasing the values of C1 and C2 by the same factor that the
frequency has been reduced. For example, the addition of a
100 pF capacitor between pin 7 (Osc) and V+ will lower the
oscillator frequency to 1 kHz from its nominal frequency of
10 kHz (multiple of 10), and thereby necessitate a
corresponding increase in the value of C1 and C2 (from
10
μ
F to 100
μ
F).
Figure 8. Lowering Oscillator Frequency
4
1
2
3
8
7
6
5
N
VOUT
+
+
COSC
C1
C2
V+
Positive Voltage Doubling
The NCP7662 may be employed to achieve positive
voltage doubling using the circuit shown in Figure 9. In this
application, the pump inverter switches of the NCP7662 are
used to charge C1
to a voltage level of V+
– VF
(where V+
is the supply voltage and VF
is the forward voltage on C1
plus
the supply voltage (V+) applied through diode D2
to
capacitor C2). The voltage thus created on C2
becomes
(2 V+) – (2 VF), or twice the supply voltage minus the
combined forward voltage drops of diodes D1
and D2.
The source impedance of the output (VOUT) will depend
on the output current, but for V+
= 5 V and an output current
of 10 mA, it will be approximately 60
.
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