Semiconductor Components Industries, LLC, 2005
January, 2005 Rev. 4
1
Publication Order Number:
NCP5210/D
NCP5210
3in1 PWM Dual Buck
and Linear DDR Power
Controller
The NCP5210, 3in1 PWM Dual Buck and Linear DDR Power
Controller, is a complete power solution for MCH and DDR memory.
This IC combines the efficiency of PWM controllers for the VDDQ
supply and the MCH core supply voltage with the simplicity of linear
regulator for the VTT termination voltage.
This IC contains two synchronous PWM buck controller for driving
four external NCh FETs to form the DDR memory supply voltage
(VDDQ) and the MCH regulator. The DDR memory termination
regulator (VTT) is designed to track at the half of the reference voltage
with sourcing and sinking current.
Protective features include, softstart circuitry, undervoltage
monitoring of 5VDUAL and BOOT voltage, and thermal shutdown.
The device is housed in a thermal enhanced spacesaving
QFN20 package.
Features
Incorporates Synchronous PWM Buck Controllers for VDDQ and
VMCH
Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A
All External Power MOSFETs are NChannel
Adjustable VDDQ and VMCH by External Dividers
VTT Tracks at Half the Reference Voltage
Fixed Switching Frequency of 250 kHz for VDDQ and VMCH
Doubled Switching Frequency of 500 kHz for VDDQ Controller in
Standby Mode to Optimize Inductor Current Ripple and Efficiency
SoftStart Protection for all Controllers
Undervoltage Monitor of Supply Voltages
Overcurrent Protections for DDQ and VTT Regulators
Fully Complies with ACPI Power Sequencing Specifications
Short Circuit Protection Prevents Damage to Power Supply Due
to Reverse DIMM Insertion
Thermal Shutdown
5x6 QFN20 Package
PbFree Package is Available*
Applications
DDR I and DDR II Memory and MCH Power Supply
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
PIN CONNECTIONS
ORDERING INFORMATION
NCP5210= Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
MARKING
DIAGRAM
COMP
FBDDQ
SS
SW_DDQ
BG_DDQ
TG_DDQ
PGND
VTT
VDDQ
AGND
FBVTT
BOOT
5VDUAL
COMP_1P5
BUF_Cut
TG_1P5
BG_1P5
GND_1P5
DDQ_REF
FB1P5
QFN20
MN SUFFIX
CASE 505AB
1
20
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NOTE: Pin 21 is the thermal pad
on the bottom of the device.
Device
Package
Shipping
NCP5210MNR2
QFN20
2500 Tape & Reel
NCP5210MNR2G
QFN20
(PbFree)
2500 Tape & Reel
1
NCP5210
AWLYYWW
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