參數(shù)資料
型號(hào): NCP502SQ34T1G
廠商: ON SEMICONDUCTOR
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: 80 mA CMOS Low Iq, Low−Dropout Voltage Regulator
中文描述: 3.4 V FIXED POSITIVE LDO REGULATOR, 1.2 V DROPOUT, PDSO5
封裝: LEAD FREE, SC-88A, SOT-353, SC-70, 5 PIN
文件頁(yè)數(shù): 7/11頁(yè)
文件大小: 101K
代理商: NCP502SQ34T1G
NCP502, NCP502A
http://onsemi.com
7
APPLICATIONS INFORMATION
A typical application circuit for the NCP502/A series is
shown in Figure 1, front page.
Input Decoupling (C1)
A 1.0
recommended and should be connected close to the
NCP502/A package. Higher values and lower ESR will
improve the overall line transient response. If large line or
load transients are not expected, then it is possible to operate
the regulator without the use of a capacitor.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K
F capacitor either ceramic or tantalum is
Output Decoupling (C2)
The NCP502/A is a stable regulator and does not require
any specific Equivalent Series Resistance (ESR) or a
minimum output current. Capacitors exhibiting ESRs
ranging from a few m up to 5.0
can thus safely be used.
The minimum decoupling value is 1.0 F and can be
augmented to fulfill stringent load transient requirements.
The regulator accepts ceramic chip capacitors as well as
tantalum devices. Larger values improve noise rejection and
load regulation transient response.
TDK capacitor: C2012X5R1C105K, C1608X5R1A105K,
or C3216X7R1C105K
Enable Operation
The enable pin will turn on the regulator when pulled high
and turn off the regulator when pulled low. These limits of
threshold are covered in the electrical specification section
of this data sheet. If the enable is not used then the pin should
be connected to V
in
.
Hints
Please be sure the Vin and GND lines are sufficiently
wide. When the impedance of these lines is high, there is a
chance to pick up noise or cause the regulator to
malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short as
possible.
Thermal
As power across the NCP502/A increases, it might
become necessary to provide some thermal relief. The
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material and also the
ambient temperature effect the rate of temperature rise for
the part. This is stating that when the NCP502/A has good
thermal conductivity through the PCB, the junction
temperature will be relatively low with high power
dissipation applications.
The maximum dissipation the package can handle is
given by:
TJ(max)
PD
TA
RJA
If junction temperature is not allowed above the
maximum 125
°
C, then the NCP502/A can dissipate up to
250 mW @ 25
°
C.
The power dissipated by the NCP502/A can be calculated
from the following equation:
Ptot
[Vin* Ignd(Iout)]
or
[Vin
Vout] * Iout
VinMAX
Ptot
Vout*Iout
Ignd
Iout
If an 80 mA output current is needed then the ground
current from the data sheet is 40 A. For an NCP502/A
(3.0 V), the maximum input voltage will then be 6.12 V.
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