參數(shù)資料
型號(hào)： NCP4331DR2G
廠商： ON SEMICONDUCTOR
元件分類： 穩(wěn)壓器
英文描述： Synchronous Buck Controller for High Efficiency Post Regulation
中文描述： SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO16
封裝： LEAD FREE, SOIC-16
文件頁(yè)數(shù)： 18/23頁(yè)
文件大小： 195K
代理商： NCP4331DR2G
NCP4331
http://onsemi.com
18
L
LOAD2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
Regulation
Block
LOAD1
HS_ DRV
VCC
VDD
LS_ DRV
GND
SYNC
BST
HB
SS
FB
Cramp
COMP
UVP
FB
VIN_FORWARD
Forward
Driver
(e.g.
NCP1280)
V
in
R
u
R
u
R
sync
V
out2
R
S
(Coil Series
Resistor)
V
out1
Figure 26. “Basic” Configuration Further Including an Overvoltage Protection (OVP)
CSin+
CSin-
CSout
+
R
OVP2
R
OVP1
CS
in
-
VCC
FB
FB
CSin-
Compared to the “basic” configuration, Figure 26 further includes an OVP feature that utilizes the auxiliary operational
amplifier (OPAMP2). Two resistors R
ovp1
and R
ovp2
scale down the output voltage and the resulting portion of V
out2
is applied
to the inverting input of OPAMP2. The non inverting input receives the feedback signal that nominally equates the internal
reference voltage (V
REF
). Hence, V
REF
also serves as the OVP reference. R
ovp1
and R
ovp2
must be dimensioned so that
OPAMP2 “triggers” when V
out2
exceeds its maximum acceptable level. The output of OPAMP2 (“CSout” that is SINK only)
is connected to the COMP pin to reduce the duty-cycle in case of OVP. CSout can be connected to the soft-start pin if a low
duty-cycle re-start-up is preferred after an OVP event. It can be noted that both options offer a protection if the feedback is
accidentally grounded since in this case, the pin6 voltage and hence, the OVP threshold are close to zero. Ultimately, the
post-regulator is protected in this fault condition.
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