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參數(shù)資料
| 型號： | NBXDPA017LN1TAG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK XO 156.25/312.5MHZ 6CLCC |
| 產(chǎn)品培訓(xùn)模塊： | XO Replacement Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PureEdge™ |
| 類型： | 振蕩器 - 晶體 |
| 頻率： | 156.25MHz，312.5MHz |
| 電源電壓： | 2.375 V ~ 3.63 V |
| 電流 - 電源： | 85mA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 6-CLCC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 供應(yīng)商設(shè)備封裝： | 6-CLCC（7x5） |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NBXDPA017LN1TAGOSDKR |
NBXDPA017
http://onsemi.com
2
FSEL
OE
GND
CLK
VDD
CLK
1
2
3
6
5
4
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
OE
LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
2
FSEL
LVTTL/LVCMOS
Control Input
Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output
Frequency Select pin description Table 3.
3
GND
Power Supply
Ground 0 V
4
CLK
LVDS Output
NonInverted Clock Output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5
CLK
LVDS Output
Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across
differential pair.
6
VDD
Power Supply
Positive power supply voltage. Voltage should not exceed 2.5 V ±5% or 3.3 V ±10%.
Table 2. OUTPUT ENABLE TRISTATE FUNCTION
OE Pin
Output Pins
Open
Active
HIGH Level
Active
LOW Level
High Z
Table 3. OUTPUT FREQUENCY SELECT
FSEL Pin
Output Frequency (MHz)
Open
(pin will float high)
156.25
HIGH Level
156.25
LOW Level
312.5
Table 4. ATTRIBUTES
Characteristic
Value
Input Default State Resistor
170 kW
ESD Protection
Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VDD
Positive Power Supply
GND = 0 V
4.6
V
Iout
LVDS Output Current
Continuous
Surge
25
50
mA
TA
Operating Temperature Range
40 to +85
°C
Tstg
Storage Temperature Range
55 to +120
°C
Tsol
Wave Solder
See Figure 6
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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| NBXDPA017LNHTAG | 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 XO LVDS 156.25/312.5 RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| NBXDPA017LU1TAG | 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 3.3V LVPECL Ethernet, Networking RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| NBXDPA018 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5 V / 3.3 V, 155.52 MHz / 311.04MHz LVDS Clock Oscillator |
| NBXDPA018_0910 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5 V / 3.3 V, 155.52 MHz / 311.04MHz LVDS Clock Oscillator |
| NBXDPA018LN1TAG | 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 3.3V LVPECL SONET, SDH, Telecom RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
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