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參數(shù)資料
| 型號： | NB7VPQ16MMNTXG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COPPER/CABLE DVR PROG 16-QFN |
| 標準包裝： | 3,000 |
| 邏輯類型： | CML 驅動器，帶可選均衡器接收器 |
| 電源電壓： | 1.71 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
NB7VPQ16M
http://onsemi.com
10
CASCADE APPLICATION
SDOUT/SCLKOUT
SDOUT is the Serial Data output pin; SCLKOUT is the
Serial Clock output pin. These pins are the outputs of the
5bit SDI shift register and will produce the SDIN/SCLKIN
signals after five serial clock cycles, see Figure 12. The
purpose of SDOUT and SCLKOUT is for use in cascade
applications, described below.
Figure 12. Simplified Cascaded Serial Data/Clock Timing Diagram
DUTA
DUTB
D3
D2
D1
D0
EQEN
SDIN
SCLKIN
SDOUT
SCLKOUT
SDIN
SCLKIN
SDOUT
SCLKOUT
D2
D1
D0
EQEN
D3
12345
5
6
789
5 Clocks
Cascaded Applications
The NB7VPQ16M can be cascaded with multiple
NB7VPQ16Ms
in
series
for
various
Equalizer/PreEmphasis applications, as shown in
Figure 13.
Serial Data In, SDINA, is clocked with SCLKINA into the
cascaded chain of the PreEmphasis and equalizer shift
registers, (DUTA, DUTB and DUTC), 5bits per register.
Upon the rising edge of the 5th clock of SCLKINA, the first
valid data bit (D3) and 5th clock will exit DUTA from
SDOUTA and SCLKOUTA and will be present at SDINB
and SCLKINB of DUTB and so on.
When SLOAD is brought LOW, the PE shift registers of
all devices are enabled and data is written into the
NB7VPQ16Ms with the contents of the PE shift registers.
When the data transfer is complete, SLOAD is brought
HIGH and all NB7VPQ16Ms are updated simultaneously.
After the PE control bits are clocked into their appropriate
registers, the LowtoHigh transition of SLOAD will latch
the data bits for the PreEmphasis DACs.
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