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參數(shù)資料
| 型號(hào)： | NB7L72MMNHTBG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SW 2X2 DIFF 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 2:2 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.3 V ~ 3.6 V |
| 電流 - 電源： | 135mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
NB7L72M
http://onsemi.com
2
VT1 SEL1 GND VCC
VT0 SEL0 GND VCC
Q0
Q1
IN0
IN1
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L72M
Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
SEL0*
SEL1*
Q0
Q1
L
IN0
L
H
IN0
IN1
H
L
IN1
IN0
H
IN1
*Defaults HIGH when left open
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IN0
LVPECL, CML,
LVDS Input
Noninverted Differential Input. (Note 1)
2
IN0
LVPECL, CML,
LVDS Input
Inverted Differential Input. (Note 1)
3
IN1
LVPECL, CML,
LVDS Input
Inverted Differential Input. (Note 1)
4
IN1
LVPECL, CML,
LVDS Input
Noninverted Differential Input. (Note 1)
5
VT1
Internal 50 W Termination Pin for IN1 and IN1.
6
SEL1
LVCMOS Input
Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth
Table; pin defaults HIGH when left open.
7
GND
Negative Supply Voltage
8
VCC
Positive Supply Voltage
9
Q1
CML Output
Noninverted Differential Output. (Note 1)
10
Q1
CML Output
Inverted Differential Output. (Note 1)
11
Q0
CML Output
Inverted Differential Output. (Note 1)
12
Q0
CML Output
Noninverted Differential Output. (Note 1)
13
VCC
Positive Supply Voltage
14
GND
Negative Supply Voltage
15
SEL0
LVCMOS Input
Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth
Table; pin defaults HIGH when left open.
16
VT0
Internal 50 W Termination Pin for IN0 and IN0
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heatsinking
conduit. The pad is electrically connected to the die, and is recommended to be electrically and
thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INx/INx input, then the device will be susceptible to selfoscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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