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參數(shù)資料
| 型號： | NB4L858MFAG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH DUAL 32LQFP |
| 標準包裝： | 250 |
| 功能： | 交叉點開關 |
| 電路： | 2 x 2:2 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.3 V ~ 3.6 V |
| 電流 - 電源： | 130mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-LQFP（7x7） |
| 包裝： | 托盤 |
NB4L858M
http://onsemi.com
6
Symbol
Characteristic
40
°C
25
°C
85
°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
fin ≤ 2 GHz
(See Figure 2)
fin ≤ 3 GHz
fin ≤ 3.5GHz
280
235
170
365
310
220
280
235
170
365
310
220
280
235
170
365
310
220
mV
fDATA
Maximum Operating Data Rate
3
Gb/s
tPLH,
tPHL
Propagation Delay to Output Differential
D/D to Q/Q
220
350
450
220
350
450
220
350
450
ps
tSWiITCH
SELyx to Valid Qyx Output (Note 9)
0.5
1.0
0.5
1.0
0.5
1.0
ns
tSKEW
Within Device Skew (Note 5)
Within Device Skew (Note 6)
Device to Device Skew (Note 9)
12
25
100
12
25
100
12
25
100
ps
tJITTER
RMS Random Clock Jitter (Note 8)
fin =2 GHz
fin =3 GHz
PeaktoPeak Data Dependent Jitter fin =2.5Gb/s
(Note 9)
fin =3.2Gb/s
Crosstalk Induced RMS Jitter (Note 11)
0.5
1.0
2.0
10
0.5
1.0
5.0
10
0.5
1.0
2.0
10
0.5
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration)
100
800
100
800
100
800
mV
tr
tf
Output Rise/Fall Times @ 0.5 GHz
Qx, Qx
(20% 80%)
80
120
80
120
80
120
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% 80%).
5. Worstcase difference between QA0 and QA1 from either DA0 or DA1 (or between QB0 and QB1 from either DB0 or DB1 respectively),
when both outputs come from the same input.
6. Worstcase difference between QA and QB outputs, when DA or DB inputs are shorted.
7. Additive RMS jitter with 50% duty cycle input clock signal.
8. Additive peaktopeak data dependent jitter with input NRZ data signal.
9. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
10. LVTTL/LVCMOS input edge rate less than 1.5 ns
11. Data taken on the same device under identical condition.
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature
0
50
100
150
200
250
300
350
400
1
1.5
2
2.5
3
3.5
VOL
T
AGE
(mV)
INPUT CLOCK FREQUENCY (GHz)
25
°C
40
°C
85
°C
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