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參數(shù)資料
| 型號： | N74F579N,602 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 0K |
| 描述： | IC COUNTER 8BIT BINARY 20DIP |
| 標準包裝： | 720 |
| 系列： | 74F |
| 邏輯類型： | 二進制計數(shù)器 |
| 方向： | 上，下 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 復位： | 異步 |
| 計時： | 同步 |
| 計數(shù)速率： | 115MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-DIP |
| 包裝： | 管件 |
| 其它名稱： | 933781130602 N74F579N N74F579N-ND |
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
2
2000 Dec 18
853-0377 25265
FEATURES
Fully synchronous operation
Multiplexed 3-State I/O ports for bus oriented applications
Built in cascading carry capability
U/D pin to control direction of counting
Separate pins for Master reset and Synchronous operation
Center power pins to reduce effects of package inductance
Count frequency 115 MHz Typ
Supply current 100 mA Typ
See 74F269 for 24-pin separate I/O port version
See 74F779 for 16-pin version
DESCRIPTION
The 74F579 is a fully synchronous 8-stage Up/Down Counter with
multiplexed 3-State I/O ports for bus-oriented applications. It
features a preset capability for programmable operation, carry
look-ahead for easy cascading and a U/D input to control the
direction of counting. All state changes, except for the case of
asynchronous reset, are initiated by the rising edge of the clock.
TC output is not recommended for use as a clock or asynchronous
reset due to the possibility of decoding spikes.
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
CP
I/O0
I/O1
I/O2
I/O3
GND
I/O4
I/O5
I/O6
I/O7
VCC
MR
SR
CEP
CET
TC
PE
CS
OE
U/D
SF01085
ORDERING INFORMATION
TYPE
TYPICAL fMAX
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F579
115MHz
100 mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5 V ±10%,
Tamb = 0 to +70 °C
PKG DWG #
20-Pin Plastic DIP
N74F579N
SOT146-1
20-Pin Plastic SOL
N74F579D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH / LOW
I/O
Data Inputs
3.5/1.0
70
A / 0.6 mA
I/On
Data Outputs
150/40
3.0 mA / 24 mA
PE
Parallel Enable input (active Low)
1.0/1.0
20
A/ 0.6 mA
U/D
Up/Down count control input
1.0/1.0
20
A / 0.6 mA
MR
Master Reset input (active Low)
1.0/1.0
20
A / 0.6 mA
SR
Synchronous Reset input (active Low)
1.0/1.0
20
A / 0.6 mA
CEP
Count Enable Parallel input (active Low)
1.0/1.0
20
A / 0.6 mA
CET
Count Enable Trickle input (active Low)
1.0/1.0
20
A / 0.6 mA
CS
Chip Select input (active Low)
1.0/1.0
20
A / 0.6 mA
OE
Output Enable input (active Low)
1.0/1.0
20
A / 0.6 mA
CP
Clock input (active Rising Edge)
1.0/1.0
20
A/ 0.6 mA
TC
Terminal Count Output (active Low)
50/33
1.0 mA / 20 mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20
A in the High state and 0.6 mA in the Low state.
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