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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 14/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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14
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Interrupt Register: IR (Reg09h), R/W, default=00h
Bit
9.0
Symbol
FRAGI*
Description
Fragment Counter Interrupt : Set to assert the interrupt when the host DMA Fragment
Counter is less than current received packet length. Writing 1 to this bit will clear the bit
and the interrupt. Writing 0 has no effect.
Receive OK Interrupt : Set to assert the interrupt. Writing 1 to this bit will clear the bit and
the interrupt. Writing 0 has no effect. The assertion timing of RI can be programmed
through the Reg50.4 bit (RINTSEL) for either the completion of the host receive DMA
activity or the completion of the receive local DMA activity.
Transmit OK Interrupt: Set to assert the interrupt. Writing 1 to this bit will clear the bit and
the interrupt. Writing 0 has no effect.
Receive Error Interrupt: Set to assert the interrupt when the packet is received with error
. Writing 1 to this bit will clear the bit and the interrupt. Writing 0 has no effect. The
assertion timing of RI can be programmed through the Reg50.4 bit (RINTSEL) for either
the completion of the host receive DMA activity or the completion of the receive local
DMA activity.
Transmit Error Interrupt : Set to assert the interrupt when the packet is transmitted with
error. Writing 1 to this bit will clear the bit and the interrupt. Writing 0 has no effect.
FIFO Error Interrupt: Set to assert the interrupt when either the TX FIFO is overrun or the
RX FIFO is overrun. Writing 1 to this bit will clear the bit and the interrupt. Writing 0 has
no effect.
Bus Error Interrupt: Set to assert the interrupt when the Bus integrity check is enabled
and failed. Writing 1 to this bit will clear the bit and the interrupt. Writing 0 has no effect.
RX Buffer Full Interrupt: Set to assert the interrupt when the RX buffer area is being
overwritten by new received packets. Writing 1 to this bit will clear the bit and the inter-
rupt. Writing 0 has no effect.
9.1
RI*
9.2
TI*
9.3
REI*
9.4
TEI*
9.5
FIFOEI*
9.6
BUSEI*
9.7
RBFI*
Note : All page pointer bits [11:0] are mapped to MA[19:8] with the same bit ordering.
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| MX98742 | FEBC 100 Base Fast Ethernet Bridge Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98728EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
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