參數(shù)資料
型號(hào): MX98715AL
英文描述: SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)卡控制器
文件頁數(shù): 12/32頁
文件大小: 215K
代理商: MX98715AL
12
P/N:PM0537
REV. 1.2, FEB. 24, 1999
MX98715A
5.2 HOST INTERFACE REGISTERS
MX98715A CSRs are located in the host I/O or memory address space. The CSRs are double word aligned and 32
bits long. Definitions and address for all CSRs are as follows :
CSR Mapping
Register
Meaning
Offset from CSR Base
Address ( PBIO and PBMA )
00
08h
10h
18h
20h
28h
30h
38h
40h
48h
50h
58h
60h
68h
70h
78h
80h
A0h
CSR0
CSR1
CSR2
CSR3
CSR4
CSR5
CSR6
CSR7
CSR8
CSR9
CSR10
CSR11
CSR12
CSR13
CSR14
CSR15
CSR16
CSR20
Bus mode
Transmit poll demand
Receive poll demand
Receive list demand
Transmit list base address
Interrupt status
Operation mode
Interrupt enable
Missed frame counter
Serial ROM and MII management
Reserved
General Purpose timer
10 Base-T status port
SIA Reset Register
10 Base-T control port
Watchdog timer
Magic Packet Register
NWay Status Register
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