參數(shù)資料
型號: MX7828LCWI+T
廠商: Maxim Integrated Products
文件頁數(shù): 8/12頁
文件大?。?/td> 0K
描述: IC ADC 8BIT HS 28-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
位數(shù): 8
采樣率(每秒): 400k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 75mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________________________________________________________________________________
5
Reference Output (2.5V) for MAX154.
Test point for MX7824. Do not connect.
REF OUT
TP
5
Three-State Data Output, bit 0 (LSB)
DBO
6
Three-State Data Output, bit 1
DB1
7
Analog Input Channel 1
AIN1
4
Analog Input Channel 2
AIN2
3
PIN
Analog Input Channel 3
AIN3
2
Analog Input Channel 4
AIN4
1
FUNCTION
NAME
_____________________________________________________________Pin Descriptions
Three-State Data Output, bit 2
DB2
8
Three-State Data Output, bit 3
DB3
9
Read Input.
R
D
controls conversions
and data access. See
Digital Interface
section.
R
D
10
Three-State Data Output, bit 7 (MSB)
DB7
20
Ground
GND
12
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to VREF+.
VREF-
13
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See
Digital Interface section.
INT
11
Chip-Select Input.
C
S
must be low for
the device to be selected.
C
S
16
Three-State Data Output, bit 4
DB4
17
Three-State Data Output, bit 5
DB5
18
Three-State Data Output, bit 6
DB6
19
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See
Digital Interface section.
INT
13
Ground
GND
14
Analog Input Channel 2
AIN2
5
Analog Input Channel 1
AIN1
6
Reference Output (2.5V) for MAX158.
Test point for MX7828. Do not connect.
REF OUT
TP
7
Analog Input Channel 3
AIN3
4
Analog Input Channel 4
AIN4
3
PIN
Analog Input Channel 5
AIN5
2
Analog Input Channel 6
AIN6
1
FUNCTION
NAME
Three-State Data Output, bit 0 (LSB)
DB0
8
Three-State Data Output, bit 1
DB1
9
Three-State Data Output, bit 2
DB2
10
Three-State Data Output, bit 3
DB3
11
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to VREF+.
VREF-
15
Read Input.
R
D
controls conversions
and data access. See
Digital Interface
section.
R
D
12
Ready Output. Open-drain output with
no active pull-up device. Goes low
when
C
S
goes low and high imped-
ance at the end of a conversion.
RDY
17
Power-Supply Voltage, +5V
VDD
26
Channel Address 2 Input
A2
23
Channel Address 1 Input
A1
24
Channel Address 0 Input
A0
25
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: VREF- to VDD.
VREF+
14
Ready Output. Open-drain output with
no active pull-up device. Goes low
when
C
S
goes low and high imped-
ance at the end of a conversion.
RDY
15
Power-Supply Voltage, +5V
VDD
24
Channel Address 1 Input
A1
21
Channel Address 0 Input
A0
22
No Connect
NC
23
Three-State Data Output, bit 7 (MSB)
DB7
22
Chip-Select Input.
C
S
must be low for
the device to be selected.
C
S
18
Three-State Data Output, bit 4
DB4
19
Three-State Data Output, bit 5
DB5
20
Three-State Data Output, bit 6
DB6
21
Analog Input Channel 8
AIN8
27
Analog Input Channel 7
AIN7
28
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: VREF- to VDD.
VREF+
16
MAX154
MX7824
MAX158
MX7828
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