參數(shù)資料
型號(hào): MX7575TQ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs
中文描述: 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP18
封裝: CERDIP-18
文件頁數(shù): 7/12頁
文件大?。?/td> 105K
代理商: MX7575TQ
the μP, in that data can be accessed independently of
the clock. The output latches are normally updated on
the rising edge of
BUSY
. But if
CS
and
RD
are low
when
BUSY
goes high, the data latches are not updat-
ed until one of these inputs returns high. Additionally,
the MX7576 stops converting and
BUSY
stays high until
RD
or
CS
goes high. This mode of operation allows a
simple interface to the μP.
Processor Interface for Signal Acquisition (MX7575)
In many applications, it is necessary to sample the
input signal at exactly equal intervals to minimize errors
due to sampling uncertainty or jitter. In order to achieve
this objective with the previously discussed interfaces,
the user must match software delays or count the num-
ber of elapsed clock cycles. This becomes difficult in
interrupt-driven systems where the uncertainty in inter-
rupt servicing delays is another complicating factor.
The solution is to use a real-time clock to control the
start of a conversion. This should be synchronous with
the CLK input to the ADC (both should be derived from
the same source), because the sampling instants occur
three clock cycles after
CS
and
RD
go low. Therefore,
the sampling instants occur at exactly equal intervals if
the conversions are started at equal intervals. In this
scheme, the output data is fed into a FIFO latch, which
allows the μP to access data at its own rate. This guar-
antees that data is not read from the ADC in the middle
of a conversion. If data is read from the ADC during a
conversion, the conversion in progress may be dis-
turbed, but the accessed data that belonged to the pre-
vious conversion will be correct.
The track/hold starts holding the input on the third
falling edge of the clock after
CS
and
RD
go low. If
CS
and
RD
go low within 20ns of a falling clock edge, the
ADC may or may not consider this falling edge as the
first of the three edges that determine the sampling
instant. Therefore, the
CS
and
RD
should not be
allowed to go low within this period when sampling
accuracy is required.
M
CMOS , μP-Compatible, 5μs/10μs, 8-Bit ADCs
_______________________________________________________________________________________
7
Figure 7. MX7575/MX7576 to Z-80 ROM Interface
ADDRESS
DECODE
ADDRESS BUS
+5V
DATA BUS
Z-80
MREQ
RD
RD
CS
EN
TP/MODE
D7
D0
DB7
DB0
MX7575*
MX7576
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 8. MX7575/MX7576 to TMS32010 ROM Interface
ADDRESS
DECODE
ADDRESS BUS
+5V
DATA BUS
PA2
PA0
MEN
DEN
RD
CS
EN
TP/MODE
D7
D0
DB7
DB0
MX7575*
MX7576
TMS32010
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 9. MX7576 Asynchronous Conversion Mode Timing
Diagram
CS
RD
BUSY
DATA
IMBUS
IMBUS
VALID
DATA
t
1
t
5
t
4
t
3
t
7
HIGH-IMPEDANCE BUS
VALID
DATA
UPDATE
LATCH
DEFER
UPDATING
ADDRESS
ENCODE
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
8085A
A0–A15
RD
RD
CS
MODE
D0–D7
ALE
AD0–AD7
MX7576*
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 10. MX7576 to 8085A Asynchronous Conversion Mode
Interface
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MX7576 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS.µ.P Compatible.5µ.s/10µ.s.8-Bit ADCs
MX7576AQ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MX7576BQ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit Precision DAC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MX7576D 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs