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參數(shù)資料
| 型號(hào)： | MX7575BQ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP18 |
| 封裝： | CERDIP-18 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 105K |
| 代理商： | MX7575BQ |
M
including the 8085A-2, test the status of the READY
input immediately after the start of an instruction cycle.
Therefore, if the MX7575/MX7576 are to be effective in
placing the μP in a wait state, their
BUSY
output should
go low very early in the cycle. When using the 8085A-2,
the earliest possible indication of an upcoming read
operation is provided by the S0 status signal. Thus, S0,
which is low for a read cycle, should be connected to
the
RD
input of the MX7575/MX7576. Figure 4 shows
the connection diagram for the 8085A-2 to the
MX7575/MX7576 in slow-memory interface mode.
ROM Interface Mode
Figure 5 shows the timing diagram for ROM interface
mode. In this mode, the μP does not need to be placed
in a wait state. A conversion is started with a read
instruction (
RD
and
CS
go low), and old data is
accessed. The
BUSY
signal then goes low to indicate
the start of a conversion. As before, the MX7575
track/hold acquires the signal on the third falling clock
edge after
RD
goes low, while the MX7576 samples it
eight times during a conversion. At the end of a conver-
sion (
BUSY
going high), another read instruction always
accesses the new data and normally starts a second
conversion. However, if
RD
and
CS
go low within one
external clock period of
BUSY
going high, then the sec-
ond conversion is not started. Furthermore, for correct
operation in this mode,
RD
and
CS
should not go low
before
BUSY
returns high.
Figures 6 and 7 show the connection diagrams for
interfacing the MX7575/MX7576 in the ROM interface
mode. Figure 6 shows the connection diagram for the
6502/6809 μPs, and Figure 7 shows the connections for
the Z-80.
Due to their fast interface timing, the MX7575/MX7576
will interface to the TMS32010 running at up to 18MHz.
Figure 8 shows the connection diagram for the
TMS32010. In this example, the MX7575/MX7576 are
mapped as a port address. A conversion is initiated by
using an IN A and a PA instruction, and the conversion
result is placed in the TMS32010 accumulator.
Asynchronous Conversion Mode (MX7576)
Tying the MODE pin low places the MX7576 into a con-
tinuous conversion mode. The
RD
and
CS
inputs are
only used for reading data from the converter. Figure 9
shows the timing diagram for this mode of operation,
and Figure 10 shows the connection diagram for the
8085A. In this mode, the MX7576 looks like a ROM to
CMOS , μP-Compatible, 5μs/10μs, 8-Bit ADCs
6
_______________________________________________________________________________________
Figure 3. Slow-Memory Interface Timing Diagram
CS
RD
BUSY
DATA
IMBUS
IMBUS
OLD
NEW
t
1
t
5
t
CONV
t
2
t
3
t
6
t
7
Figure 4. MX7575/MX7576 to 8085A-2 Slow-Memory Interface
ADDRESS
DECODE
ADDRESS BUS
+5V
DATA BUS
ADDRESS
LATCH
8085A-2
A8–A15
S0
RD
CS
TP/MODE
BUSY
D0–D7
ALE
AD0–AD7
READY
MX7575*
MX7576
* SOME CIRCUITRY OMITTED FOR CLARITY
S0 IS LOW FOR READ CYCLES
Figure 5. ROM Interface Timing Diagram
CS
RD
BUSY
DATA
IMHIGH-
BUS
HIGH-
IMPBUS
OLD
DATA
t
1
t
5
t
4
t
2
t
3
t
7
HIGH-IMPEDANCE BUS
NEW
DATA
t
8
t
3
t
7
Figure 6. MX7575/MX7576 to 6502/6809 ROM Interface
ADDRESS
DECODE
ADDRESS BUS
+5V
DATA BUS
6502-6809
A0–A15
R/W
Φ
2 OR E
RD
CS
EN
TP/MODE
D0–D7
D0–D7
MX7575*
MX7576
* SOME CIRCUITRY OMITTED FOR CLARITY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MX7575D | 16-Bit Ultra-Low-Power Microcontroller, 32kB OTP, 1KB RAM, USART, HW multiplier, 120 segment LCD 100-QFP -40 to 85 |
| MX7575J | 16-Bit Ultra-Low-Power Microcontroller, 32kB OTP, 1KB RAM, USART, HW multiplier, 120 segment LCD 100-QFP -40 to 85 |
| MX7575JN | CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs |
| MX7575JP | CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs |
| MX7575KCWN | CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX7575D | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs |
| MX7575J | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs |
| MX7575J/D | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs |
| MX7575JCWN | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MX7575JCWN+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit Precision DAC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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