
MVTX2802
Data Sheet
25
Zarlink Semiconductor Inc.
6.2 Frame Engine Details
This section briefly describes the functions of each of the modules of the MVTX2802AG frame engine.
6.2.1 FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame
departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values
can be determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging, and
for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the
bootstrap pin and the aging time is defined in register FCBAT.
6.2.2 Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a
switch request.
6.2.3 RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each
frame for use by the search engine when the switch request has been made.
6.2.4 TxQ Manager
First, the TxQ manager checks the per-class queue status and global Reserved resource situation, and using
this information, makes the frame dropping decision after receiving a switch response. If the decision is not to
drop, the TxQ manager requests that the FCB manager link the unicast frame’s FCB to the correct
per-port-per-class TxQ. If multicast, the TxQ manager writes to the multicast queue for that port and class. The
TxQ manager can also trigger source port flow control for the incoming frame’s source if that port is flow control
enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the
queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads
the FCB information and writes to the correct port control module.
6.3 Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also
writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the
port control module requests that the buffer be released.
6.4 TxDMA
The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from
the port control modules.
7.0 Quality of Service and Flow Control
7.1 Model
Quality of service (QoS) is an all-encompassing term for which different people have different interpretations. In
this chapter, by quality of service assurances, we mean the allocation of chip resources so as to meet the
latency and bandwidth requirements associated with each traffic class. We do not presuppose anything about
the offered traffic pattern. If the traffic load is light, then ensuring quality of service is straightforward. But if the
traffic load is heavy, the MVTX2802AG must intelligently allocate resources so as to assure quality of service for
high priority data.