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參數(shù)資料
| 型號： | MTV112M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded CRT Monitor Controller Flash Version |
| 中文描述： | CRT顯示器8051嵌入式控制器Flash版本 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 160K |
| 代理商： | MTV112M |
MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
Revision 2.0 - 11 - 2001/05/18
VCNTH
(r) :
V-Freq counter's high bits.
= 1
→
V-Freq counter overflows; this bit is cleared by H/W when condition removed.
High bit of V-Freq counter.
Vovf
VF8 :
VCNTL
(r) :
V-Freq counter's low bits.
PCTR0
(w) :
SYNC processor control register 0.
C1, C0 = 1,1
→
Selects CVSYNC as the polarity, Freq and VBLANK source.
= 1,0
→
Selects VSYNC as the polarity, Freq and VBLANK source.
= 0,0
→
Disables composite function (MTV012 compatible mode).
= 0,1
→
H/W auto switches to CVSYNC when CVpre=1 and VSpre=0.
HVsel
= 1
→
Pin #16 is P4.1, pin #17 is P4.0.
= 0
→
Pin #16 is HBLANK, pin #17 is VBLANK.
STOsel = 1
→
Pin #29 is P4.2.
= 0
→
Pin #29 is STOUT.
PREFS = 0
→
Selects 8MHz OSC as H/V presence check and self-test pattern time base.
= 1
→
Selects 12MHz OSC as H/V presence check and self-test pattern time base.
HALFV = 1
→
VBLANK is half frequency output of VSYNC.
HBpl
= 1
→
Negative polarity HBLANK output.
= 0
→
Positive polarity HBLANK output.
VBpl
= 1
→
Negative polarity VBLANK output.
= 0
→
Positive polarity VBLANK output.
PCTR2
(w) :
Self-test pattern generator control.
= 1
→
Enables generator.
= 0
→
Disables generator.
STbsh = 1
→
63.5KHz (horizontal) output selected.
= 0
→
31.75KHz (horizontal) output selected.
Rt1, Rt0= 0,0
→
Positive cross-hatch pattern output.
= 0,1
→
Negative cross-hatch pattern output.
= 1,0
→
Full white pattern output.
= 1,1
→
Full black pattern output.
STF
= 1
→
Enables STOUT output.
= 0
→
Disables STOUT output.
PCTR3
(w) :
HSYNC clamp pulse control register.
ENCLP = 1
→
pin #4 is HCLAMP.
= 0
→
pin #4 is P1.3.
CLPEG = 1
→
Clamp pulse follows HSYNC leading edge.
= 0
→
Clamp pulse follows HSYNC trailing edge.
CLPPO= 1
→
Positive polarity clamp pulse output.
= 0
→
Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] X 0.25 μs for 8MHz X’tal selection,or
[(CLPW2:CLPW0) + 1] X 0.167 μs for 12MHz X’tal selection.
EHALFV= 1
→
pin #2 is HALFV.
= 0
→
pin #2 is P1.1.
EHALFV= 1
→
pin #3 is HALFH.
= 0
→
pin #3 is P1.2.
Selft
P4OUT
(w) :
Port 4 data output value.
P5OUT
(r/w) :
Port 5 data input/output value.
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