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參數資料
| 型號： | MT93L16 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low-Voltage Acoustic Echo Canceller(低電壓回聲消除器) |
| 中文描述： | 低電壓聲回波消除器（低電壓回聲消除器） |
| 文件頁數： | 8/27頁 |
| 文件大小： | 118K |
| 代理商： | MT93L16 |
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MT93L16
Preliminary Information
8
Table 2 - ST-BUS & GCI Mode Select
SSI Operation
The SSI PCM interface consists of data input pins
(Rin, Sin), data output pins (Sout, Rout), a variable
rate bit clock (BCLK), and two enable pins (ENA1,
ENA2) to provide strobes for data transfers. The
active high enable may be either 8 or 16 BCLK
cycles in duration. Automatic detection of the data
type (8 bit companded or 16 bit 2’s complement
linear) is accomplished internally. The data type
cannot change dynamically from one frame to the
next.
In SSI operation, the frame boundary is determined
by the rising edge of the ENA1 enable strobe (see
Figure 7). The other enable strobe (ENA2) is used
for parsing input/output data and it must pulse within
125 microseconds of the rising edge of ENA1.
In SSI operation, the enable strobes may be a mixed
combination of 8 or 16 BCLK cycles allowing the
flexibility to mix 2’s complement linear data on one
port (e.g., Rin/Sout) with companded data on the
other port (e.g., Sin/Rout).
Table 3 - SSI Enable Strobe Pins
PCM Law and Format Control (LAW, FORMAT)
The PCM companding/coding law used by the
MT93L16 is controlled through the LAW and
FORMAT pins. ITU-T G.711 companding curves for
μ
-Law and A-Law are selected by the LAW pin. PCM
coding ITU-T G.711 and Sign-Magnitude are
selected by the FORMAT pin. See Table 4.
PORT1
Rin/Sout
ST-BUS/GCI Mode
Selection
PORT2
Sin/Rout
Enable Pins
Enable Pins
MD1
ENA1
MD2
ENA2
0
0
Mode 1. 8 bit companded PCM I/O on
timeslot 0
0
0
0
1
Mode 2. 8 bit companded PCM I/O on
timeslot 2.
0
1
1
0
Mode 3. 8 bit companded PCM I/O on
timeslot 2. Includes D & C channel
bypass in timeslots 0 & 1.
1
0
1
1
Mode 4. 16 bit 2’s complement linear
PCM I/O on timeslots 0 & 1.
1
1
Enable Strobe Pin
Designated PCM I/O Port
ENA1
Line Side Echo Path (PORT 1)
ENA2
Acoustic Side Echo Path (PORT 2)
Figure 6 - ST-BUS and GCI 16-Bit 2’s complement linear PCM I/O (Mode 4)
C4i
F0i (stbus)
Rin
Sout
7 6 5 4 3 2 1 0
Sin
Rout
PORT1
PORT2
S141312 1110 9 8
ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and
PORT2 need not necessarily both be in mode 4.
outputs = High impedance
inputs = don’t care
7 6 5 4 3 2 1 0
S141312 1110 9 8
7 6 5 4 3 2 1 0
S141312 1110 9 8
7 6 5 4 3 2 1 0
S141312 1110 9 8
F0i (GCI)
start of frame (stbus & GCI)
EC
EC
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