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參數資料
| 型號： | MT9300 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| 中文描述： | 多通道語音回聲消除器（多通道話音回聲消除器） |
| 文件頁數： | 10/29頁 |
| 文件大?。?/td> | 110K |
| 代理商： | MT9300 |
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MT9300
Advance Information
10
When
configuration is selected, Control Register A1/B1 and
Control Register 2 of the selected group of echo
cancellers require special care. Refer to the Register
description section.
Extended
Delay
or
Back-to-Back
Table 2 is a list of the channels used for the 16
groups of echo cancellers when they are configured
as
Extended Delay
or
Back-to-Back
Normal Configuration
For a given group (group 0 to 15), 2 PCM I/O
channels are used. For example, group 1 Echo
Cancellers A and B, channels 2 and 3 are active.
Extended Delay Configuration
For a given group (group 0 to 15), only one PCM I/O
channel is active (Echo Canceller A) and the other
channel carries don’t care data. For example, group
2, Echo Canceller A (Channel 4) will be active and
Echo Canceller B (Channel 5) will carry don’t care
data.
Back-to-Back Configuration
For a given group (group 0 to 15), only one PCM I/O
channel is active (Echo Canceller A) and the other
channel carries don’t care data. For example, group
5, Echo Canceller A (Channel 10) will be active and
Echo Canceller B (Channel 11) will carry don’t care
data.
Figure 8 - Memory Mapping
Power Up Sequence
On power up, the RESET pin must be held low for
100
μ
s. Forcing the RESET pin low will put the
MT9300 in power down state. In this state, all
internal clocks are halted, D<7:0>, Sout, Rout, DTA
and IRQ pins are tristated. The 16 Main Control
Registers, the Interrupt FIFO Register and the Test
Register are reset to zero.
When the RESET pin returns to logic high and a
valid MCLK is applied, the user must wait 500
μ
s for
PLL to lock. C4i and F0i can be active during this
period. Once the PLL has locked, the user must
power up the 16 groups of echo cancellers
individually, by writing a “1” into the PWUP bit in
each group of echo canceller’s Main Control
Register.
For each group of echo cancellers, when the PWUP
bit toggles from zero to one, echo cancellers A and B
execute their initialization routine. The initialization
routine sets their registers, Base Address+00
H
to
Base Address+3F
H
, to the default Reset Value and
clears the Adaptive Filter coefficients. Two frames
are necessary for the initialization routine to execute
properly.
Once the initialization routine is executed, the user
can set the per channel Control Registers, Base
Address+00
H
to Base Address+3F
H
, for the specific
application.
Group
Channel
Group
Channel
0
0, 1
8
16, 17
1
2, 3
9
18, 19
2
4, 5
10
20, 21
3
6, 7
11
22, 23
4
8, 9
12
24, 25
5
10, 11
13
26, 27
6
12, 13
14
28, 29
7
14, 15
15
30, 31
Table 2 - Group and Channel allocation
0000h -->
Channel 0, EC A Ctrl/Stat Registers
001Fh
0020h -->
Channel 1, EC B Ctrl/Stat Registers
003Fh
0040h -->
Channel 2, EC A Ctrl/Stat Registers
005Fh
0060h -->
Channel 3, EC B Ctrl/Stat Registers
007Fh
03C0h -->
Channel 30, EC A Ctrl/Stat Registers
03DFh
03E0h -->
Channel 31, EC B Ctrl/Stat Registers
03FFh
0400h --> 040Fh
Main Control Registers <15:0>
Group 0
Echo
Cancellers
Registers
Groups 2 --> 14
Echo Cancellers
Registers
Group 1
Echo
Cancellers
Registers
Group 15
Echo
Cancellers
Registers
0410h
Interrupt FIFO Register
0411h
Test Register
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PDF描述 |
|---|---|
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| MT93L16 | Low-Voltage Acoustic Echo Canceller(低電壓回聲消除器) |
| MTD2955V-1 | 30V N-Channel PowerTrench MOSFET |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MT9300AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BL | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BV | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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