參數(shù)資料
型號: MT9196AP1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡
英文描述: Integrated Digital Phone Circuit (IDPC)
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC28
封裝: LEAD FREE, PLASTIC, MS-018AB, LCC-28
文件頁數(shù): 3/46頁
文件大?。?/td> 631K
代理商: MT9196AP1
MT9196
Data Sheet
3
Zarlink Semiconductor Inc.
Overview
The functional block diagram of Figure 1 depicts the main operations performed by the MT9196 IDPC. Each of
these functional blocks will be described individually in the sections to follow. This overview will describe some of
the end-user features which may be implemented as a direct result of the level of integration found within the IDPC.
The main feature required of a digital telephone is to convert the digital Pulse Code Modulated (PCM) information,
being received by the telephone set, into an analog electrical signal. This signal is then applied to an appropriate
audio transducer such that the information is finally converted into intelligible acoustic energy. The same is true of
the reverse direction where acoustic energy is converted first into an electrical analog and then digitized (into PCM)
before being transmitted from the set. Along the way if the signals can be manipulated, either in the analog or the
digital domains, other features such as gain control and signal generation may be added. Finally, most electro-
acoustic transducers (loudspeakers) require a large amount of power if they are to develop an acoustic signal. The
inclusion of audio amplifiers to provide this power is required.
14
D
out
Data Output.
A tri-state digital output for 8 bit wide channel data being sent to the Layer 1
device. Data is shifted out via this pin concurrent with the rising edge of BCL during the
timeslot defined by STB, or according to standard ST-BUS timing.
15
D
in
Data Input.
A digital input for 8 bit wide channel data received from the Layer 1 device. Data
is sampled on the falling edge of BCL during the timeslot defined by STB, or according to
standard ST-BUS timing. Input level is CMOS compatible.
16
STB/F0i
Data Strobe/Frame Pulse (Input).
For SSI mode this input determines the 8 bit timeslot
used by the device for both transmit and receive data. This active high signal has a repetition
rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS mode. CMOS level
compatible input.
17
CLOCKin
Clock Input.
The clock provided to this input is used by the internal phone functions. In ST-
BUS mode this is the C4i input. In SSI synchronous mode, this is the Bit Clock input. In SSI-
asynchronous mode this is an asynchronous 4 MHz Master Clock input.
18
XSTL2
Crystal Input (4.096 MHz).
Used in conjunction with the CLOCKin pin to provide the master
clock signal via external crystal.
19
V
DD
Positive Power Supply (Input).
Nominally 5 volts.
20
HSPKR-
Inverting Handset Speaker (Output).
Output to the handset speaker (balanced).
21
HSPKR+
Non-Inverting Handset Speaker (Output).
Output to the handset speaker (balanced).
22
SPKR-
Inverting Speaker (Output).
Output to the speakerphone speaker (balanced).
23
SPKR+
Non-Inverting Speaker (Output).
Output to the speakerphone speaker (balanced).
24
V
SS
SPKR
Power Supply Rail for Speaker Driver.
Nominally 0 Volts.
AUX
out
Auxiliary Port (Output).
Access point to the D/A (analog) signals of the receive path as well
as to the various analog inputs.
25
26
AUX
in
Auxiliary Port (Input).
An analog signal may be fed to the filter/codec transmit section and
various loopback paths via this pin. No external anti-aliasing is required.
27
MIC+
Non-inverting on-hook answer back Microphone (Input).
Microphone amplifier non-
inverting input pin.
28
V
SSA
Analog Ground (Input).
Nominally 0 V.
Pin Description (continued)
Pin #
Name
Description
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