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參數(shù)資料
| 型號(hào)： | MT9172APR |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQCC28 |
| 封裝： | PLASTIC, MS-018AB, LCC-28 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 552K |
| 代理商： | MT9172APR |
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MT9171/72
Data Sheet
20
Zarlink Semiconductor Inc.
Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Notes:
1)
When operating as a SLAVE the C4 clock has a 40% duty cycle.
2)
When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,
F
C
=2.5xf
C4
). The relative phase between these two clocks (
Φ
in Fig. 17) is not critical and may vary from
0 ns to t
C4P
. However, the relative jitter must be less than J
C
(see Figure 17).
Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams
Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode
Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode
AC Electrical Characteristics
- Clock Timing - DN Mode (Figures 16 & 17)
Characteristics
Sym.
Min.
Typ.*
Max.
Units
Test Conditions
1
C4 Clock Period
t
C4P
244
ns
2
C4 Clock Width High or Low
t
C4W
122
ns
In Master Mode - Note 1
3
Frame Pulse Setup Time
t
F0S
50
ns
4
Frame Pulse Hold Time
t
F0H
50
ns
5
Frame Pulse Width
t
F0W
244
ns
6
10.24 MHz Clock Jitter (wrt C4)
J
C
±15
ns
Note 2
Channel 31
Bit 0
Channel 0
Bit 7
Channel 0
Bit 6
F0
C4
ST-BUS
BIT CELLS
C4
F0
2.0V
0.8V
2.0V
0.8V
t
C4P
t
C4W
t
F0S
t
F0H
t
F0W
t
C4W
C4
OSC1
2.0V
0.8V
3.0V
2.0V
J
C
Φ
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