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參數(shù)資料
| 型號： | MT9172AP1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, MS-018AB, LCC-28 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 552K |
| 代理商： | MT9172AP1 |
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MT9171/72
Data Sheet
3
Zarlink Semiconductor Inc.
9
10
12
CDSTi/
CDi
Control/Data ST-BUS In/Control/Data In
(Digital). A 2.048 Mbit/s serial control
& signalling input in DN mode. In MOD mode this is a continuous bit stream at
the bit rate selected.
Control/Data ST-BUS Out/Control/Data Out
(Digital). A 2.048 Mbit/s serial
control & signalling output in DN mode. In MOD mode this is a continuous bit
stream at the bit rate selected.
Negative Power Supply
(0 V).
DSTo/Do
Data ST-BUS Out/Data Out
(Digital). A 2.048 Mbit/s serial PCM/data output in
DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.
DSTi/Di
Data ST-BUS In/Data In
(Digital). A 2.048 Mbit/s serial PCM/data input in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
10
11
13
CDSTo/
CDo
11
12
12
13
14
15
V
SS
13
14
16
14
15
17
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device
to allow daisy chaining. In MOD mode provides the receive bit rate clock to the
system.
15
16
19
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible
clock input for the MASTER and output for the SLAVE in DN mode. For MOD
mode this pin provides the transmit bit rate clock to the system.
Oscillator Output
. CMOS Output.
Oscillator Input
. CMOS Input. D.C. couple signals to this pin. Refer to D.C.
Electrical Characteristics for OSC1 input requirements.
Precanceller Disable.
When held to Logic ’1
’,
the internal path from L
OUT
to the
precanceller is forced to V
Bias
thus bypassing the precanceller section. When
logic ’0’, the L
OUT
to the precanceller path is enabled and functions normally. An
internal pulldown (50 k
) is provided on this pin.
No Connection.
Leave open circuit
16
17
17
19
21
22
OSC2
OSC1
18
20
23
Precan
8,
18
1,6,
11,
18,
20,
25
24
NC
19
21
L
OUT
DIS
L
OUT
Disable.
When held to logic “1”, L
OUT
is disabled (i.e., output = V
Bias
). When
logic “0”, L
OUT
functions normally. An internal pulldown (50 k
) is provided on
this pin.
TEST
Test Pin.
Connect to V
SS
.
L
IN
Receive Signal
input (Analog).
V
DD
Positive Power Supply
(+5 V) input.
20
21
22
22
23
24
26
27
28
Pin Description (continued)
Pin #
Name
Description
22
24
28
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9172APR | 制造商:Microsemi Corporation 功能描述:DNIC 1.5UM - Tape and Reel |
| MT9172APR1 | 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:PB FREE DNIC 1.5UM - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SUBSCRIBER NETWRK DNIC 28PLCC 制造商:Microsemi Corporation 功能描述:IC SUBSCRIBER NETWRK DNIC 28PLCC |
| MT9173 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB |
| MT9173AE | 制造商:Microsemi Corporation 功能描述:DGTL INTRFC CIRCUIT 24DIP - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC SUBSCRIBER NETWRK DSIC 24PDIP |
| MT9173AE1 | 制造商:Microsemi Corporation 功能描述:DGTL INTRFC CIRCUIT 24DIP - Rail/Tube |
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