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參數(shù)資料
| 型號(hào)： | MT9092 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Digital Telephone with HDLC(數(shù)字電話（帶高階數(shù)據(jù)鏈路控制HDLC）) |
| 中文描述： | 數(shù)字電話（數(shù)字電話（帶高階數(shù)據(jù)鏈路控制的HDLC）與的HDLC） |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 278K |
| 代理商： | MT9092 |
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MT9092
7-18
All data transfers through the microport are two-byte
transfers requiring the transmission of a Command/
Address byte followed by the data byte written or
read from the addressed register. CS must remain
asserted for the duration of this two-byte transfer. As
shown in Figure 6, the falling edge of CS indicates to
the HPhone-
II
that a microport transfer is about to
begin. The first 8 clock cycles of SCLK after the
falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and of what address. The
next 8 clock cycles are used to transfer the data byte
between the HPhone-
II
and the microcontroller. At
the end of the two-byte transfer CS is brought high
again to terminate the session. The rising edge of
CS will tri-state the output driver of DATA1 which will
remain tri-stated as long as CS is high.
Receive data is sampled and transmit data is made
available on DATA1 concurrent with the falling edge
of SCLK.
An open-drain interrupt request (IRQ) output
provides a method for interrupting the microcontroller
when an unmasked HDLC event occurs within the
HPhone-
II
. IRQ remains active until the HDLC
Interrupt Status Register is read or a (hardware/
software) reset occurs. More detail is provided in the
section pertaining to the HDLC functional block.
Lastly, provision is made to seperate the transmit
and receive data streams onto two individual pins.
This control is given by the DATASEL pin in the
General Control Register (address 0Fh). Setting
DATASEL logic high will cause DATA1 to become the
data receive pin and DATA2 to become the data
transmit pin. Only the signal paths are altered by
DATASEL; internal timing remains the same in both
cases. Tri-stating on DATA2 follows CS as it does on
DATA1 when DATASEL is logic low. Use of the
DATASEL bit is intended to help in adapting Motorola
(SPI) and National Semiconductor (Micro-wire)
microcontrollers to the HPhone-
II
. Note that whereas
Intel processor serial ports transmit data LSB first
other processor serial ports, including Motorola,
transmit data MSB first. It is the responsibility of the
microcontroller to provide LSB first data to the
HPhone-
II
.
ST-BUS/Timing Control
A serial link is required for the transport of data
between the HPhone-
II
and the external digital
transmission device. The HPhone-
II
utilizes the ST-
BUS architecture defined by Mitel Semiconductor.
Refer to Mitel Application Note MSAN-126. The
HPhone-
II
ST-BUS consists of output and input
serial data streams, DSTo and DSTi respectively, a
synchronous clock signal C4i, and a framing pulse
F0i.
Figure 6 - Serial Port Relative Timing
D
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R/W
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0
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS
DATA 1
Receive
DATA 1 or DATA 2
Transmit
SCLK
CS
Delays due to MCS-51 internal timing which are transparent.
The HPhone-II: -latches received data on the falling edge of SCLK
-outputs transmit data on the falling edge of SCLK
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
6 bits - Addressing Data
1 bit - Not used, write logic "0"
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9092 | ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II) |
| MT9094 | Digital Telephone (DPhone-II)(數(shù)字電話) |
| MT9122 | Dual Voice Echo Canceller with Tone Detection(雙話音回聲消除器（帶音調(diào)檢測(cè)功能）) |
| MT9122AE | CMOS Dual Voice Echo Canceller with Tone Detection |
| MT9122AP | CMOS Dual Voice Echo Canceller with Tone Detection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9092AP | 制造商:Microsemi Corporation 功能描述: |
| MT9092AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:DGTL TEL 44PLCC - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE H-PHONE-PLUS PLCC |
| MT9092APR | 制造商:Microsemi Corporation 功能描述:DGTL TEL 44PLCC - Tape and Reel |
| MT9092APR1 | 制造商:Microsemi Corporation 功能描述:DGTL TEL 44PLCC - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL TELEPHONE CIRCUIT 44PLCC 制造商:Microsemi Corporation 功能描述:IC DGTL TELEPHONE CIRCUIT 44PLCC |
| MT9094 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone (DPhone-II) |
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