參數(shù)資料
型號: MT9080B
廠商: Mitel Networks Corporation
英文描述: SMX - Switch Matrix Module(用于消費類轉(zhuǎn)換應用的開關矩陣模塊)
中文描述: SMX -開關矩陣模塊(用于消費類轉(zhuǎn)換應用的開關矩陣模塊)
文件頁數(shù): 13/25頁
文件大小: 123K
代理商: MT9080B
CMOS
MT9080B
2-113
Switching any input channel to an output channel
timeslot is possible by merely writing the address of
the input channel in the Connection Memory location
corresponding to the output channel timeslot. For
example, to switch channel 1 to output channel 5 and
enable output drivers during channel 5, the
Connection Memory location corresponding to
channel 5 should be loaded with Hex 2001. This
word will be clocked out of the Connection Memory
during timeslot 4 and will cause the Data Memory to
clock out contents of the memory corresponding to
channel 1 during the channel 5 timeslot. The 16 bit
word clocked out by the Connection Memory will also
enable Data Memory output drivers, and, external
drivers.
2048 Channel Switch Matrix
A
interchange switch can be constructed with three
SMXs as shown in Figure 18. SMX#1 and SMX#2
are used to store data and switch it in time, while the
third SMX functions as a Connection Memory.
2048
channel,
double
buffered
timeslot
SMX#1 and 2 are operated in the Counter Mode and
External Mode alternatively in consecutive frames. In
any specific frame, one of the two is in Counter mode
while the other is in External mode. The functions
are reversed in the successive frame. The SMX in
counter mode is programmed to write data
Figure 18 - 2048 Channel Timeslot Interchange Circuit
CM-2
SMX #3
D11
D0o-D10o
ODE
Mz
My
Mx
FP
CK
+5
C16
MPU Interface
CONNECTION
MEMORY
U2
U1
11
11
+5
16
16
16
C16
+5
C16
C16
16
D0-D15i
CK
FP
Mz
R/W
ODE
A0-A10
ME
D0-D15o
Mx
My
CS
DS
CNT/EXT
SMX #1
D0-D15i
CK
FP
Mz
R/W
ODE
A0-A10
ME
D0-D15o
Mx
My
CS
DS
CNT/EXT
SMX #2
Data
Output
DATA
MEMORY
DATA
MEMORY
Timing
Generator
DFP
CFP
16.384 MHz
Notes:
1)
2)
U1 and U2 are required if the data output bus is to be enabled/disabled via the microprocessor interface.
All inputs not shown should be connected to Ground (V
SS
).
D
D
R
C
A
C
D
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