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參數(shù)資料
| 型號： | MT9076AB |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/J1 3.3V Single Chip Transceiver |
| 中文描述： | T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器 |
| 文件頁數(shù)： | 95/160頁 |
| 文件大?。?/td> | 416K |
| 代理商： | MT9076AB |
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Preliminary Information
MT9076
91
20.2.1
Per Channel Receive signaling (T1 and E1 mode) (Pages 9 and 0AH)
Page 09H, addresses 10000 to 11111, and page 1AH addresses 10000 to 10111 contain the Receive signaling
Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 85 illustrates the mapping between the
addresses of these pages and the DS1 channel numbers. Table 86 describes bit allocation within each of these
registers.
Page 9 Address:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Equivalent DS1
channel
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Page A Address:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Equivalent DS1
channel
17
18
19
20
21
22
23
24
x
x
x
x
x
x
x
x
Table 84 - Page 9, A Address Mapping to DS1 Channels (T1)
Bit
Name
Functional Description
7 - 4
- - -
Unused
3
A(n)
Receive signaling Bits A for Channel n
. These bits are extracted from bit position 8 of
every channel in received frame 6 (within the 12 frame superframe structure for D4
superframes and the 24 frame structure for ESF superframes). The bits may be debounced
for 6 to 9 milliseconds where control bit DBNCE is set high.
3
B(n)
Receive signaling Bits B for Channel n
. These bits are extracted from bit position 8 of
every channel in received frame 12 (within the 12 frame superframe structure for D4
superframes and the 24 frame structure for ESF superframes). The bits may be debounced
for 6 to 9 milliseconds where control bit DBNCE is set high.
2
C(n)
Receive signaling Bits C for Channel n
. These bits are extracted from bit position 8 of
every channel in received frame 18 within the 24 frame structure for ESF superframes. The
bits reported may be debounced for 6 to 9 milliseconds where control bit DBNCE is set high.
In D4 mode these bits are unused.
0
D(n)
Receive signaling Bits D for Channel n
. These bits are extracted from bit position 8 of
every channel in received frame 24 within the 24 frame structure for ESF superframes. The
bits reported may be debounced for 6 to 9 milliseconds where control bit DBNCE is set high.
In D4 mode these bits are unused.
Table 85 - Receive Channel Associated signaling (Pages 9 and A) (T1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器) |
| MT9079 | Advanced Controller for E1(先進(jìn)的E1幀調(diào)節(jié)器和控制器) |
| MT9080B | SMX - Switch Matrix Module(用于消費類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊) |
| MT90810 | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9076AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver |
| MT9076BB | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
| MT9076BB1 | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
| MT9076BP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver |
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