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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 8/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
8
List of Tables
Table 1 -
Table 2 -
Table 3 -
Table 4 -
Table 5 -
Table 6 -
Table 7 -
Table 8 -
Table 9 -
Table 10 - Effect of PSEL Field on P-byte Generation.......................................................................................53
Table 11 - Register Summary ............................................................................................................................82
Table 12 - Main Control Register .......................................................................................................................84
Table 13 - Main Status Register.........................................................................................................................84
Table 14 - Window to External Memory Register - CPU....................................................................................85
Table 15 - Read Parity Register.........................................................................................................................85
Table 16 - Memory Configuration Register ........................................................................................................86
Table 17 - TX_SAR Control Register.................................................................................................................87
Table 18 - TX_SAR Status Register...................................................................................................................87
Table 19 - TX_SAR Scheduler Base Register ...................................................................................................88
Table 20 - TX_SAR Frame End Register...........................................................................................................88
Table 21 - TX_SAR End Ratio Register.............................................................................................................88
Table 22 - TX_SAR Control Structure Base Address Register..........................................................................89
Table 23 - Transmit Data Cell FIFO Base Address Register .............................................................................89
Table 24 - Transmit Data Cell FIFO Write Pointer Register...............................................................................89
Table 25 - Transmit Data Cell FIFO Read Pointer Register...............................................................................90
Table 26 - RX_SAR Control Register.................................................................................................................91
Table 27 - RX_SAR Status Register..................................................................................................................92
Table 28 - RX_SAR Misc. Event ID Register.....................................................................................................92
Table 29 - RX_SAR Misc. Event Counter Register............................................................................................92
Table 30 - RX_SAR Underrun Event ID Register...............................................................................................93
Table 31 - RX_SAR Underrun Event Counter Register .....................................................................................93
Table 32 - RX_SAR Overrun Event ID Register.................................................................................................93
Table 33 - RX_SAR Overrun Event Counter Register .......................................................................................93
Table 34 - UTOPIA Control Register..................................................................................................................94
Table 35 - UTOPIA Status Register...................................................................................................................94
Table 36 - VPI / VCI Concatenation Register.....................................................................................................95
Table 37 - VPI Match Register...........................................................................................................................95
Table 38 - VPI Mask Register ............................................................................................................................95
Table 39 - VCI Match Register...........................................................................................................................95
Table 40 - VCI Mask Register............................................................................................................................96
Table 41 - VPI Timing Register..........................................................................................................................96
Table 42 - VCI Timing Register..........................................................................................................................96
Table 43 - Lookup Table Base Address Register...............................................................................................96
Table 44 - Receive Data Cell FIFO Base Address Register ..............................................................................97
Table 45 - Receive Data Cell FIFO Write Pointer Register................................................................................97
Table 46 - Receive Data Cell FIFO Read Pointer Register................................................................................97
Table 47 - TDM Interface Control Register ........................................................................................................98
Table 48 - TDM Interface Status Register..........................................................................................................99
Primary UTOPIA Bus Pins................................................................................................................19
Secondary UTOPIA Bus Pins ...........................................................................................................20
Microprocessor Bus Interface Pins ...................................................................................................20
External Memory Interface Pins........................................................................................................21
Master Clock, Test, and Power Pins.................................................................................................22
TDM Port Pins...................................................................................................................................23
Reset State of I/O and Output Pins...................................................................................................24
Pinout Summary................................................................................................................................25
Memory Size Combinations..............................................................................................................39
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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