- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383644 > MT90500 (Mitel Networks Corporation) Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) PDF資料下載
參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū)（多通道自動(dòng)柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口）） |
| 文件頁(yè)數(shù)： | 32/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)
MT90500
32
4.1.2
TDM Interface Operation
4.1.2.1
Main TDM Bus Operation
The main TDM bus (pins ST[15:0]) supports SCSA, MVIP, H-MVIP, ST-BUS, and IDL protocols. These buses
have different frame sync pulse orientations and different data sampling specifications, as well as different pin
requirements. However, all of these buses are composed of 16 data pins, as well as CLKx2, CLKx1, and
FSYNC lines.
The TDM bus type is controlled by the TDM Bus Type Register at 6010h. In all bus types, outputs change on
the rising edge of CLKx1. Inputs can be sampled at the 2/4, 3/4 or 4/4 point of the CLKx1 signal. MVIP/SCSA/
ST-BUS all use a negative FSYNC that is asserted for one CLKx2 cycle, straddling the frame boundary. The
IDL bus uses a positive FSYNC which is asserted for one cycle of CLKx1, preceding the frame boundary. (See
Figure 39, “Nominal TDM Bus Timing,” on page 114.)
4.1.2.2
TDM Loopback
The General Output Enable bit (GENOE in the TDM Interface Control Register at 6000h) is used to enable data
to be driven out on the TDM output streams. When this bit it not set (i.e. it is LOW), the internal TDM transmit
buses are connected to the internal TDM receive buses (while the internal TDM buses are disconnected from
the external TDM buses) giving a TDM loopback from ATM receive back to ATM transmit. In this mode, the
internally-generated TDM clocks and synchronization signals are used. This allows the user to test the
MT90500 in stand-alone mode by passing receive ATM cells through the SAR, through the internal loopback at
the TDM interface, and back through the SAR and out as transmit ATM cells.
4.1.2.3
Per-channel Output Enable Feature
The ST[15:0] pins are bidirectional, and are able to switch between input and output directions on a per-
channel basis. The Output Enable Registers located at addresses 7000 + 2N (N = 0, 1, ..., 127) are used for
individual time slot output enable control. Depending on the TDM bus rate, up to 128 registers (256 bytes) are
used to provide up to 2048 individual channel-output-enable bits. At 2.048 Mbps, 32 registers are used; at
4.096 Mbps, 64 registers are used; and at 8.192 Mbps, 128 registers are used.
During each channel period (TDM time slot), 16 output enable bits (one register) are read from the Output
Enable Registers. Within each frame, 32, 64, or 128 registers are read (depending on the TDM bus rate). The
GENOE bit must be set HIGH, as well as the individual channel-output-enable bit, in order for a TDM channel
to be transmitted from the MT90500 onto the TDM bus. In order to prevent data collisions on the TDM bus, the
user should clear all Output Enable Register bits for channels not used as outputs, prior to setting the GENOE
bit. The GENOE signal, when inactive, asynchronously deactivates the tristate buffers on the data pins and
routes the output paths back into the input paths, causing the TDM bus to enter the TDM Loopback mode (see
Section 4.1.2.2).
Since the ST pins are bidirectional, the input sampling is always active and output data can be re-sampled back
into the MT90500. This re-sampling is used when LOCSTi channels are output on a ST pin and then re-
sampled for ATM transmission, when ST outputs are re-sampled for transfer to the LOCSTo pin, or for test and
verification purposes.
4.1.2.4
Local Bus Operation
The local bus signals are:
LOCx2, LOCx1, LSYNC - clock output signals;
LOCSTi, LOCSTo - Local Serial TDM data in and data out.
The MT90500 provides three output clocks for the local TDM bus: LOCx2, LOCx1 and LSYNC. These clocks
are derived from CLKx2, and controlled by the relevant bits in the Local Bus Type Register (register 6020h).
The LCLKDIV bits allow LOCx2 to be equal to CLKx2, CLKx2 / 2, or CLKx2 / 4 (note that the local bus rate is
2.048 Mbps, which is always equal to, or less than, the main TDM bus rate). Also in register 6020h are the
control bits to select the LSYNC frame-pulse type, the routing of TDM streams onto and from the local bus, and
the LOCSTi sampling point.Except for the rate, the local bus type can be configured independently of the main
TDM bus type.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500 | Multi-Channel ATM AAL1 SAR |
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。