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參數(shù)資料
| 型號： | MT89L80AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Digital Switch |
| 中文描述： | 意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字開關(guān) |
| 文件頁數(shù)： | 11/15頁 |
| 文件大小： | 75K |
| 代理商： | MT89L80AP |
Advance Information
MT89L80
2-13
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
AC Electrical Characteristics
- Serial Streams (Figures 11, 12 and 13)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
O
U
T
P
U
T
S
STo0/7 Delay - Active to High Z
t
SAZ
5
55
ns
R
L
=1 K
*
, C
L
=150 pF
2
STo0/7 Delay - High Z to Active
t
SZA
5
55
ns
C
L
=150 pF
3
STo0/7 Delay - Active to Active
t
SAA
5
55
ns
C
L
=150 pF
R
L
=1 K
*
, C
L
=150 pF
4
Output Driver Enable Delay
t
OED
50
ns
5
External Control Delay
t
XCD
55
ns
C
L
=150 pF
6
I
N
Serial Input Setup Time
t
SIS
20
ns
7
Serial Input Hold Time
t
SIH
20
ns
Figure 11 - Serial Outputs and External Control
Figure 12 - Output Driver Enable
Figure 13 - Serial Inputs
C4i
STo0
to
STo7
STo0
to
STo7
STo0
to
STo7
CSTo
Bit Cell Boundary
t
SAZ
t
SZA
t
SAA
t
XCD
*
*
V
HM
V
LM
V
HM
V
LM
V
HM
V
LM
V
HM
V
LM
V
HM
V
LM
ODE
STo0
to
STo7
*
t
OED
t
OED
*
V
HM
V
LM
V
HM
V
LM
Bit Cell Boundaries
C4i
STi0
to
STi7
t
SIS
t
SIH
V
HM
V
LM
V
HM
V
LM
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