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參數(shù)資料
| 型號： | MT8924AS |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | PCM Conference Circuit (PCC) Preliminary Information |
| 中文描述： | 會議的PCM電路（PCC）的初步信息 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 102K |
| 代理商： | MT8924AS |
MT8924
Preliminary Information
8-4
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
TD
Tone Duration (Input).
When TD is High, a PCM-coded tone is sent out to all channels of
the enabled conferences instead of PCM data. TD is latched by frame pulse F0i so that all
channels have the same tone during the same frame number. When TD is Low, normal
operation is enabled.
2
TF
Tone Frequency (Input).
This input is connected to an external squarewave generator. TF
is strobed by frame pulse F0i so that all channels have the same tone frequency during the
same number of frames. The PCM-coded tone level corresponds to 1/10th of the full scale
value, and is activated when TD is High.
3
RESET
Master RESET (Input).
This input is used for system reset after power up, or when the
companding law format has been changed. The RESET pin is strobed by the rising edge of
clock Cki. Complete circuit initialization takes two frame periods. Resetting the device
disables the output drivers of the microprocessor interface and DSTo.
4
OS
Overflow Signalling (Output).
When OS is Low, a conference is in the overflow condition.
This signal is delayed by half of a timeslot relative to the beginning of the output channel of
the conference in overflow (see Figure 9).
5
DST
o
ST-BUS Serial Output.
This pin is the output for the PCM signal. It is enabled upon
channel selection, otherwise it is placed in a high impedance state. Maximum bit rate is
2.048 Mb/s.
6-13
D7 to D0
Data Bus I/O Port.
These are bidirectional data pins over which data and instructions are
transferred to and from the microprocessor (where D0 is the least significant bit). The bus is
in a high impedance state when RESET is Low and/or CS is High.
14
V
DD
C/D
Positive Supply Voltage.
Nominally 5 volts.
15
Control/Data Select (Input).
The signal on this input defines whether the information on the
data bus should be interpreted as opcode or data. During a write operation a Low signal
defines the bus content as data, while a High signal defines it as opcode. During a read
operation this input differentiates overflow status between the first eight channels for C/D
being LOW, and the last two channels for C/D being HIGH (see Instruction 4). This input also
allows status monitoring (see Instruction 6) during a read operation.
16
CS
Chip Select (Input).
This active low input selects the device for microprocessor read/write
operations. When CS is Low, data and instructions can be transferred to or from the
microprocessor, and when CS is High, the data bus is in a high impedance state.
17
RD
Read (Input).
This active low input is for the read signal on the microprocessor interface.
The data bus is updated on the falling edge of RD.
18
WR
Write Input.
This active low input is for the write signal on the microprocessor interface. The
data bus is strobed on the rising edge of WR.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
TD
TF
RESET
OS
D7
D6
D5
D4
D3
D2
D1
VSS
A/
μ
DSTi
Cko
Cki
F0i
WR
RD
CS
C/D
VDD
D0
DSTo
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| MT8924 | PCM Conference Circuit (PCC) Preliminary Information |
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