參數(shù)資料
型號: MT8920BE
廠商: Mitel Networks Corporation
英文描述: ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit
中文描述: 異意法半導體的CMOS總線⑩家庭圣總線并行訪問電路
文件頁數(shù): 17/24頁
文件大小: 534K
代理商: MT8920BE
CMOS
MT8920B
3-19
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C, V
DD
=5V, t
CLK
=244 ns, t
CH
=t
CL
=122 ns and are for design aid only: not guaranteed and not subject to production
testing.
The cycle is initiated by the falling edge of CS or DS, whichever occurs last. Timing is relative to the last falling edge which initiates the cycle.
(1) t
cwm
is equal to t
CH
or t
CL
whichever is smaller (some ST-BUS compatible transceivers may generate C4 clock having t
CHmin
=70ns
or t
CLmin
=70ns.
(2) Worst case access when memory contention occurs.
Figure 14 - Mode 1 Parallel Bus Timing
During Interrupt Acknowledge cycle IACK replaces CS. R/W must remain high.
AC Electrical Characteristics
- Mode 1 Parallel Bus Timing (see Fig. 14)
(V
CC
=5.0V
±
5%,T
A
=-40 to 85
°
C)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Address to DS (CS) Low
R/W to DS (CS) Low
DS (CS) Low to DTACK Low
t
ARDS
t
RWDS
t
RDS1,2
t
RD
0
ns
2
20
ns
3
t
cwm
t
cwm
-30
t
CLK
2*t
CLK
ns
Load C
4
Valid Data to DTACK Low (Read)
ns
Load A, C
L
=130pF, R
L
=740
5
DS High to DTACK High
t
DAR
t
DHZ
t
CSH
t
DHT
t
DST
65
ns
Load C, C
L
=50pF
6
DS High to Data High Imped.(Read)
0
45
ns
Load A, C
L
=130pF, R
L
=740
7
DS High to CS High
0
ns
8
Data Hold Time (Write)
0
ns
9
Input Data Valid after DS
t
cwm
-30
ns
10
Address Hold Time
t
ADHT
50
ns
A0 - A5
CS (IACK
)
R/W
DS
DTACK
D0 - D7
D0 - D7
t
ADHT
t
ARDS
t
RWDS
t
RDS
t
RD
t
DST
t
DHT
DATA IN
DATA OUT
t
DHZ
t
DAR
t
CSH
相關PDF資料
PDF描述
MT8920BP ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit
MT8920BS ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit
MT8926 ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)
MT8926AE ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)
MT8926AP ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)
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