參數(shù)資料
型號(hào): MT88E45
廠商: Mitel Networks Corporation
英文描述: 4-Wire Calling Number Identification Circuit(4線主叫識(shí)別電路(接收傳送的物理層信號(hào)))
中文描述: 4線主叫號(hào)碼識(shí)別電路(四線主叫識(shí)別電路(接收傳送的物理層信號(hào)))
文件頁(yè)數(shù): 18/27頁(yè)
文件大?。?/td> 113K
代理商: MT88E45
MT88E45
Advance Information
18
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
o
C and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. FSK input data at 1200
±
12 baud.
2. OSC1 at 3.579545 MHz
±
0.1%.
3. Function of signal condition.
AC Electrical Characteristics
- CAS Detection Timing
Characteristics
Sym
Min
Max
Units
Notes
1
Tone present detect time
t
DP
t
DA
0.5
10
ms
See Figures 16, 17
2
Tone absent detect time
0.1
8
ms
See Figures 16, 17
AC Electrical Characteristics
- 3-Wire Interface Timing
Characteristics
Sym
Min
Max
Units
Notes
1
OSC2
Power-up time
t
PU
t
PD
t
CP
t
CA
50
ms
2
Power-down time
10
ms
3
CD
Input FSK to CD low delay
25
ms
4
Input FSK to CD high delay
10
ms
5
Hysteresis
10
ms
AC Electrical Characteristics
- 3-Wire Interface Timing (Mode 0)
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
DR/STD
Rise time
t
RR
t
RF
t
RL
200
ns
into 50pF Load
2
Fall time
200
ns
into 50pF Load
3
Low time
415
416
417
μ
s
2
4
DATA
Rate
1188
1200
1212
baud
1
5
Input FSK to DATA
delay
t
IDD
1
5
ms
6
DATA
DCLK
Rise time
t
R
t
F
200
ns
into 50pF Load
7
Fall time
200
ns
into 50pF Load
8
DATA to DCLK delay
t
DCD
t
CDD
f
DCLK0
t
CH
t
CL
t
CRD
6
416
μ
s
μ
s
1, 2, 3
9
DCLK to DATA delay
6
416
1, 2, 3
10
DCLK
Frequency
1201.6
1202.8
1204
Hz
2
11
High time
415
416
417
μ
s
μ
s
μ
s
2
12
Low time
415
416
417
2
13
DCLK
DR/STD
DCLK to DR delay
415
416
417
2
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參數(shù)描述
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