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參數(shù)資料
| 型號(hào)： | MT88E41 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Extended Voltage Calling Number Identification Circuit (ECNIC)(擴(kuò)展電壓主叫識(shí)別電路（提供各種主叫線信息傳遞設(shè)備的接口）) |
| 中文描述： | 擴(kuò)展電壓主叫號(hào)碼識(shí)別電路（ECNIC）（擴(kuò)展電壓主叫識(shí)別電路（提供各種主叫線信息傳遞設(shè)備的接口）） |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大?。?/td> | 99K |
| 代理商： | MT88E41 |
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MT88E41
5-24
rising edge corresponds to the centre of each DATA
bit cell (providing the incoming baud rate matches
the DCLK rate). DCLK is not generated for the stop
and start bits. Consequently, DCLK will clock only
valid data into a peripheral device such as a serial to
parallel shift register or a micro-controller. The
ECNIC also outputs an end of word pulse (data
ready) at the DR pin. The data ready signal indicates
the reception of every 10-bit word sent from the
Central Office. This output is typically used to
interrupt a micro-controller. The three outputs
together, eliminate the need for a UART (Universal
Asynchronous Receiver Transmitter) or the high
software overhead of performing the UART function
(asynchronous serial data reception).
Note that the 3-pin interface may also output data
generated by voice since these frequencies are in
the input frequency detection band of the device.
The user may choose to ignore these outputs when
FSK data is not expected, or force the ECNIC into its
powerdown mode.
Power Down Mode
For
consumption, the ECNIC can be forced into power
down when it is not needed to receive FSK data. This
is done by pulling the PWDN pin high. In powerdown
mode, the crystal oscillator, op-amp and internal
circuitry are all disabled and the ECNIC will not react
to the input signal. DATA and DCLK are at logic high,
and DR and CD are at high impedance or at logic
high when pulled up with resistors.The ECNIC can
be awakened for reception of the FSK signal by
pulling the PWDN pin to ground (see Figure 9).
applications
requiring
reduced
power
Carrier Detect
The presence of the FSK signal is indicated by a
logic low at the carrier detect (CD) output. This
output has built in hysteresis to prevent toggling
when the received signal is shortly interrupted. Note
that the CD output is also activated by voice since
these frequencies are in the input frequency
detection band of the device. The user may choose
to ignore this output when FSK data is not expected,
or force the ECNIC into its powerdown mode.
Figure 5 - Common Crystal Connection
Crystal Oscillator
The ECNIC uses a crystal oscillator as the master
timing source for filters and the FSK demodulator.
The crystal specification is as follows:
Frequency:
Frequency tolerance:
Resonance mode:
Load capacitance:
Maximum series resistance: 150 ohms
Maximum drive level (mW): 2 mW
e.g. CTS MP036S
3.579545 MHz
±
0.1%(-40
°
C+85
°
C)
Parallel
18 pF
A number of MT88E41 devices can be connected as
shown in Figure 5 such that only one crystal is
required. The connection between OSC2 and OSC1
can be D.C. coupled as shown, or A.C. coupled using
30pF capacitors. Alternatively, the OSC1 inputs on
all devices can be driven from a CMOS buffer (dc
coupled) with the OSC2 outputs left unconnected.
VRef and CAP Inputs
V
Ref
is the output of a low impedance voltage source
equal to V
DD/2
and is used to bias the input op-amp.
A 0.1
μ
F capacitor is required between CAP and V
SS
to suppress noise on V
Ref.
OSC1
OSC2
OSC1
OSC2
OSC1
OSC2
3.579545 MHz
MT88E41
MT88E41
MT88E41
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