參數(shù)資料
型號: MT8888CN-1
廠商: Mitel Networks Corporation
英文描述: CB 3C 3#16S SKT RECP WALL
中文描述: 綜合DTMFTransceiver與英特爾微型接口
文件頁數(shù): 3/16頁
文件大?。?/td> 302K
代理商: MT8888CN-1
MT8888C/MT8888C-1
4-93
Functional Description
The
Transceiver consists of a high performance DTMF
receiver with an internal gain setting amplifier and a
DTMF generator which employs a burst counter to
synthesize precise tone bursts and pauses. A call
progress mode can be selected so that frequencies
within the specified passband can be detected. The
Intel micro interface allows microcontrollers, such as
the 8080, 80C31/51 and 8085, to access the
MT8888C/MT8888C-1 internal registers.
MT8888C/MT8888C-1
Integrated
DTMF
Input Configuration
The input arrangement of the MT8888C/MT8888C-1
provides a differential-input operational amplifier as
well as a bias source (V
Ref
), which is used to bias the
inputs at V
DD
/2. Provision is made for connection of
a feedback resistor to the op-amp output (GS) for
gain adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
Figure 4 shows the necessary connections for a
differential input configuration.
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). These
filters incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
Figure 3 - Single-Ended Input Configuration
C
R
IN
R
F
IN+
IN-
GS
V
Ref
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
MT8888C/
MT8888C-1
Figure 4 - Differential Input Configuration
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
F
LOW
F
HIGH
DIGIT
D
3
D
2
D
1
D
0
697
1209
1
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
852
1477
9
1
0
0
1
941
1336
0
1
0
1
0
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
852
1633
C
1
1
1
1
941
1633
D
0
0
0
0
C1
C2
R1
R2
R3
R4
R5
IN+
IN-
GS
V
Ref
MT8888C/
MT8888C-1
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 k
R2 = 60k
, R3 = 37.5 k
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
V
diff) - R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2
R1
2
+ (1/
ω
C)
2
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