參數(shù)資料
型號: MT8885
廠商: Mitel Networks Corporation
英文描述: Integrated DTMF Transceiver with Power Down and Adaptive Micro Interface(雙音多頻信號(DTMF)收發(fā)器(帶電源關(guān)閉和自適應(yīng)微接口))
中文描述: 集成雙音多頻收發(fā)器的斷電和自適應(yīng)微型接口(雙音多頻信號(DTMF)的收發(fā)器(帶電源關(guān)閉和自適應(yīng)微接口))
文件頁數(shù): 10/25頁
文件大?。?/td> 190K
代理商: MT8885
MT8885
Preliminary Information
4-60
Table 6. Control Register A Description
Table 7
.
Control Register B Description
Note 1: When both TOUT and RxEN are asserted to power-down, the crystal oscillator and the Vref circuits are powered down.
Bit
Name
Description
b0
TOUT
Tone Output Control. A logic high enables the tone output; a logic low puts the DTMF
transmitter in power-down mode. The TONE output pin is held in high impedance and the
transmit register is cleared. See Note 1 below.
b1
CP/DTMF
Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a rectangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2
IRQ
Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
b3
RSEL
Register Select. A logic high selects control register B for the next write cycle to the control
register address. After writing to control register B, the following control register write cycle
will be directed to control register A.
Bit
Name
Description
b0
BURST
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1
RxEN
This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic high deactivates and puts both receiver circuits into power-down mode.
See Note 1 below.
b2
S/D
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
b3
C/R
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
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