參數(shù)資料
型號: MT8880C
廠商: Mitel Networks Corporation
英文描述: Integrated DTMF Transceiver(雙音多頻信號(DTMF)收發(fā)器(帶電話程序濾波器))
中文描述: 集成雙音多頻收發(fā)器(雙音多頻信號(DTMF)的收發(fā)器(帶電話程序濾波器))
文件頁數(shù): 15/24頁
文件大?。?/td> 188K
代理商: MT8880C
ISO
2
-CMOS
MT8880C
4-47
Characteristics are over recommended operating conditions unless otherwise stated
Typical figures are at 25
°
C, V
= 5V, and for design aid only: not guaranteed and not subject to production testing
* See “Notes” AC Electrical Characteristics Tables
AC Electrical Characteristics
- Call Progress
-
Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
Lower freq. (ACCEPT)
f
LA
f
HA
f
LR
f
HR
320
Hz
@ -25 dBm
2
Upper freq. (ACCEPT)
510
Hz
@ -25 dBm
3
Lower freq. (REJECT)
290
Hz
@ -25 dBm
4
Upper freq. (REJECT)
540
Hz
@ -25 dBm
5
Call progress tone detect level
(total power)
-30
dBm
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Conditions
1
R
X
Tone present detect time
t
DP
t
DA
t
REC
t
REC
t
ID
t
DO
t
PStb3
t
PStRX
t
BST
t
PS
t
BSTE
t
PSE
V
HOUT
V
LOUT
dB
P
THD
3
11
14
ms
Note 12
2
Tone absent detect time
0.5
4
8.5
ms
Note 12
User adjustable
#
User adjustable
#
User adjustable
#
User adjustable
#
3
Tone duration accept
40
ms
4
Tone duration reject
20
ms
5
Interdigit pause accept
40
ms
6
Interdigit pause reject
20
ms
μ
s
μ
s
ms
7
Delay St to b3
13
8
Delay St to RX
0
-RX
3
Tone burst duration
8
9
T
X
50
52
DTMF mode
10
Tone pause duration
50
52
ms
DTMF mode
11
Tone burst duration (extended)
100
104
ms
Call Progress mode
12
Tone pause duration (extended)
100
104
ms
Call Progress mode
R
L
=10k
R
L
=10k
R
L
=10k
25 kHz Bandwidth
R
L
=10k
f
C
=3.579545 MHz
13
T
O
N
E
O
U
T
High group output level
-6.1
-2.1
dBm
14
Low group output level
-8.1
-4.1
dBm
15
Pre-emphasis
2
3
dB
16
Output distortion (Single Tone)
-35
dB
17
Frequency deviation
f
D
R
LT
t
CYC
t
CH
t
CL
t
R,
t
F
t
AH,
t
RWH
t
AS,
t
RWS
t
DHR
t
DDR
t
DSW
±
0.7
±
1.5
50
%
k
ns
18
Output load resistance
Φ
2 cycle period
Φ
2 high pulse width
Φ
2 low pulse width
Φ
2 rise and fall time
Address, R/W hold time
Address, R/W setup time (before
Φ
2)
Data hold time (read)
Φ
2 to valid data delay (read)
Data setup time (write)
10
19
M
P
U
I
N
T
E
R
F
A
C
E
250
20
115
ns
21
110
ns
22
25
ns
23
26
ns
24
23
ns
25
22
ns
*
26
100
ns
200 pF load
27
45
ns
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